[Intel-gfx] [PATCH 3/6] drm/i915: Enabling the TLB invalidate bit in GFX Mode register

[Chris Wilson]

On Mon, Mar 24, 2014 at 12:19:21PM +0530, sourab.gupta at intel.com wrote:
> From: Akash Goel <akash.goel at intel.com>
> 
> This patch Enables the bit for TLB invalidate in GFX Mode register
> for Gen7.
> 
> According to bspec,  When enabled this bit limits the invalidation
> of the TLB only to batch buffer boundaries, to pipe_control
> commands which have the TLB invalidation bit set and sync flushes.
> If disabled, the TLB caches are flushed for every full flush of
> the pipeline.
> 
> Signed-off-by: Akash Goel <akash.goel at intel.com>
> Signed-off-by: Sourab Gupta <sourab.gupta at intel.com>
Tested-by: Chris Wilson <chris at chris-wilson.co.uk> # ivb, hsw
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre