[Intel-gfx] [PATCH v2 6/6] drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv

[Damien Lespiau]

On Mon, Mar 24, 2014 at 11:00:07PM +0530, sourab.gupta at intel.com wrote:
> From: Akash Goel <akash.goel at intel.com>
> 
> For disabling L3 clock gating we need to set bit 25 of MMIO
> register 940c. Earlier this was being done by just writing 1
> into bit 25 and resetting all other bits.
> This patch modifies the routine to read-modify-write of the
> register, so that the values of other bits are not destroyed.
> 
> v2: Modifying the comments and the patch commit message (Chris)

This patch commit message lacks the most important information: which
bit are we setting back to 0 and we shouldn't, and why is that
important? We do direct writes to other registers in that function (for
instance (MI_ARB_VLV just below).

-- 
Damien