[Intel-gfx] [PATCH v2 4/6] drm/i915/vlv: Remove the enabling of VS_TIMER_DISPATCH bit in MI MODE reg

[sourab.gupta at intel.com]

From: Akash Goel <akash.goel at intel.com>

Removing the VS_TIMER_DISPATCH bit enable for MI MODE reg for
Gen7 platform as it is not required.

v2: Enhancing the scope of the patch to full Gen7 (Chris)

Signed-off-by: Akash Goel <akash.goel at intel.com>
Signed-off-by: Sourab Gupta <sourab.gupta at intel.com>
Tested-by: Chris Wilson <chris at chris-wilson.co.uk> # ivb, hsw -Chris
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index eb4811a..9983802 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -599,7 +599,9 @@ static int init_render_ring(struct intel_ring_buffer *ring)
 	int ret = init_ring_common(ring);
 
 	if (INTEL_INFO(dev)->gen > 3)
-		I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
+		if (!IS_GEN7(dev))
+			I915_WRITE(MI_MODE,
+					_MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 
 	/* We need to disable the AsyncFlip performance optimisations in order
 	 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
-- 
1.8.5.1