[Intel-gfx] [PATCH] drm/i915: Add OACONTROL to the command parser register whitelist.

[Jani Nikula]

On Wed, 26 Mar 2014, Kenneth Graunke <kenneth at whitecape.org> wrote:
> Mesa needs to be able to write OACONTROL in order to expose the
> Observability Architecture's performance counters via OpenGL.
>
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> ---
>  drivers/gpu/drm/i915/i915_cmd_parser.c | 1 +
>  drivers/gpu/drm/i915/i915_reg.h        | 2 ++
>  2 files changed, 3 insertions(+)
>
> This patch needs to go before
>
>    commit 6d42f94084b8c69813d7ecd0466c33fe561bf127
>    Author: Brad Volkin <bradley.d.volkin at intel.com>
>    Date:   Tue Feb 18 10:15:57 2014 -0800
>
>        drm/i915: Enable command parsing by default
>
> in whatever branch gets submitted to Dave Airlie.  Or, that commit needs
> to be reverted.  Otherwise, every OpenGL program will abort.  Examples
> of programs that abort include GNOME, KDE, Firefox, and glxgears.
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index bae7c2f..d4a50b9 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -415,6 +415,7 @@ static const u32 gen7_render_regs[] = {
>  	GEN7_SO_WRITE_OFFSET(1),
>  	GEN7_SO_WRITE_OFFSET(2),
>  	GEN7_SO_WRITE_OFFSET(3),
> +	OACONTROL,

Comment above gen7_render_regs array:

 * Register whitelists, sorted by increasing register offset.

You'll get a DRM_ERROR for this.

Daniel, naughty naughty for pushing this already!

BR,
Jani.


>  };
>  
>  static const u32 gen7_blt_regs[] = {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9f9e2b7..0ebc20d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -427,6 +427,8 @@
>  /* There are the 4 64-bit counter registers, one for each stream output */
>  #define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
>  
> +#define OACONTROL 0x2360
> +
>  #define _GEN7_PIPEA_DE_LOAD_SL	0x70068
>  #define _GEN7_PIPEB_DE_LOAD_SL	0x71068
>  #define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \
> -- 
> 1.9.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center