[Intel-gfx] [PATCH 2/3] drm/i915: Implement sema idle msg disable for all rings

[Daniel Vetter]

On Mon, Mar 31, 2014 at 06:17:17PM +0300, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Previously in
>  commit 295e8bb73a4785b65db6655fbf6ad57c4177b551
>  Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
>  Date:   Thu Feb 27 21:59:01 2014 +0200
> 
>     drm/i915: Disable semaphore wait event idle message on BDW
> 
> I failed to notice that all rings have their own copy of the bit that
> disables the semaphore wait even idle message. So that patch only succeeded
> in disabling it for the render ring. Instead we should set the bit for all
> rings.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem.c | 8 ++++++++
>  drivers/gpu/drm/i915/i915_reg.h | 2 ++
>  drivers/gpu/drm/i915/intel_pm.c | 3 ---
>  3 files changed, 10 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 33bbaa0..84a7171 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4372,6 +4372,14 @@ static int i915_gem_init_rings(struct drm_device *dev)
>  			goto cleanup_blt_ring;
>  	}
>  
> +	if (IS_GEN8(dev)) {
> +		struct intel_ring_buffer *ring;
> +		int i;
> +
> +		for_each_ring(ring, dev_priv, i)
> +			I915_WRITE(RING_RC_PSMI_CONTROL(ring),
> +				   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
> +	}

Why move this to here? Is this one of those bits which get reset on ring
init? If that's the case I think we really need to have a w/a checker to
make sure that after driver load, suspend/resume and gpu reset we always
have the same set of workarounds ...
-Daniel

>  
>  	ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
>  	if (ret)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1f927a5..a47b4c3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1068,6 +1068,8 @@ enum punit_power_well {
>  #define   GEN6_BLITTER_LOCK_SHIFT			16
>  #define   GEN6_BLITTER_FBC_NOTIFY			(1<<3)
>  
> +#define RING_RC_PSMI_CONTROL(ring) ((ring)->mmio_base + 0x50)
> +
>  #define GEN6_RC_SLEEP_PSMI_CONTROL	0x2050
>  #define   GEN8_RC_SEMA_IDLE_MSG_DISABLE	(1 << 12)
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9454a3c..21cfbc7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4876,9 +4876,6 @@ static void gen8_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(GEN7_GT_MODE,
>  		   GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
>  
> -	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
> -		   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
> -
>  	/* WaDisableSDEUnitClockGating:bdw */
>  	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
>  		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> -- 
> 1.8.3.2
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch