[Intel-gfx] [PATCH] drm/i915: Increase WM memory latency values on SNB with high pixel clock

[Robert Navarro]

Runyan, Arthur J <arthur.j.runyan <at> intel.com> writes:

> 
> Please check the DRAM configuration for the systems that fail.  The higher 
latency is more likely with
> higher tRFC which is mainly found with 8 Gbit components.
> 

What other information do we need to get this included?

The DRAM config, is this something that I have to/should check? How do I get 
this information to you?