[Intel-gfx] [PATCH 06/71] drm/i915/chv: Add PIPESTAT register bits for Cherryview

[Barbalho, Rafael]

> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces at lists.freedesktop.org] On Behalf
> Of ville.syrjala at linux.intel.com
> Sent: Wednesday, April 09, 2014 11:28 AM
> To: intel-gfx at lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 06/71] drm/i915/chv: Add PIPESTAT register bits
> for Cherryview
> 
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> FIXME: We probably want to sprinkle _CHV suffixes over these.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Reviewed-by: Rafael Barbalho <rafael.barbalho at intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index b6441da..0fb6b6f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3364,6 +3364,7 @@ enum punit_power_well {
>  #define   SPRITE1_FLIP_DONE_INT_EN_VLV		(1UL<<30)
>  #define   PIPE_CRC_ERROR_ENABLE			(1UL<<29)
>  #define   PIPE_CRC_DONE_ENABLE			(1UL<<28)
> +#define   PERF_COUNTER2_INTERRUPT_EN		(1UL<<27)
>  #define   PIPE_GMBUS_EVENT_ENABLE		(1UL<<27)
>  #define   PLANE_FLIP_DONE_INT_EN_VLV		(1UL<<26)
>  #define   PIPE_HOTPLUG_INTERRUPT_ENABLE		(1UL<<26)
> @@ -3375,8 +3376,10 @@ enum punit_power_well {
>  #define   PIPE_ODD_FIELD_INTERRUPT_ENABLE	(1UL<<21)
>  #define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE	(1UL<<20)
>  #define   PIPE_B_PSR_INTERRUPT_ENABLE_VLV	(1UL<<19)
> +#define   PERF_COUNTER_INTERRUPT_EN		(1UL<<19)
>  #define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE	(1UL<<18) /* pre-965
> */
>  #define   PIPE_START_VBLANK_INTERRUPT_ENABLE	(1UL<<18) /* 965 or
> later */
> +#define   PIPE_FRAMESTART_INTERRUPT_ENABLE	(1UL<<17)
>  #define   PIPE_VBLANK_INTERRUPT_ENABLE		(1UL<<17)
>  #define   PIPEA_HBLANK_INT_EN_VLV		(1UL<<16)
>  #define   PIPE_OVERLAY_UPDATED_ENABLE		(1UL<<16)
> @@ -3384,6 +3387,7 @@ enum punit_power_well {
>  #define   SPRITE0_FLIP_DONE_INT_STATUS_VLV	(1UL<<14)
>  #define   PIPE_CRC_ERROR_INTERRUPT_STATUS	(1UL<<13)
>  #define   PIPE_CRC_DONE_INTERRUPT_STATUS	(1UL<<12)
> +#define   PERF_COUNTER2_INTERRUPT_STATUS	(1UL<<11)
>  #define   PIPE_GMBUS_INTERRUPT_STATUS		(1UL<<11)
>  #define   PLANE_FLIP_DONE_INT_STATUS_VLV	(1UL<<10)
>  #define   PIPE_HOTPLUG_INTERRUPT_STATUS		(1UL<<10)
> @@ -3392,12 +3396,16 @@ enum punit_power_well {
>  #define   PIPE_DPST_EVENT_STATUS		(1UL<<7)
>  #define   PIPE_LEGACY_BLC_EVENT_STATUS		(1UL<<6)
>  #define   PIPE_A_PSR_STATUS_VLV			(1UL<<6)
> +#define   PIPE_LEGACY_BLC_EVENT_STATUS		(1UL<<6)
>  #define   PIPE_ODD_FIELD_INTERRUPT_STATUS	(1UL<<5)
>  #define   PIPE_EVEN_FIELD_INTERRUPT_STATUS	(1UL<<4)
>  #define   PIPE_B_PSR_STATUS_VLV			(1UL<<3)
> +#define   PERF_COUNTER_INTERRUPT_STATUS		(1UL<<3)
>  #define   PIPE_HOTPLUG_TV_INTERRUPT_STATUS	(1UL<<2) /* pre-965
> */
>  #define   PIPE_START_VBLANK_INTERRUPT_STATUS	(1UL<<2) /* 965 or
> later */
> +#define   PIPE_FRAMESTART_INTERRUPT_STATUS	(1UL<<1)
>  #define   PIPE_VBLANK_INTERRUPT_STATUS		(1UL<<1)
> +#define   PIPE_HBLANK_INT_STATUS		(1UL<<0)
>  #define   PIPE_OVERLAY_UPDATED_STATUS		(1UL<<0)
> 
>  #define PIPESTAT_INT_ENABLE_MASK		0x7fff0000
> --
> 1.8.3.2
> 
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