[Intel-gfx] [PATCH 1/3] drm/i915: consider the source max DP lane count too

[Damien Lespiau]

On Tue, May 06, 2014 at 02:34:41PM +0100, Damien Lespiau wrote:
> On Tue, May 06, 2014 at 02:56:50PM +0300, Jani Nikula wrote:
> > From: Paulo Zanoni <paulo.r.zanoni at intel.com>
> > 
> > Even if the panel claims it can support 4 lanes, there's the
> > possibility that the HW can't, so consider this while selecting the
> > max lane count.
> > 
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> > Signed-off-by: Jani Nikula <jani.nikula at intel.com>
> 
> Note that we also have an eDP lane count in the VBT we may want to factor
> in here as well.

Ah, that's what this series is all about, discard this comment then.

-- 
Damien