[Intel-gfx] [Mesa-dev] [rong.r.yang at intel.com: How user space applications load registers on HSW?]

[Kenneth Graunke]

On 05/06/2014 08:26:15 AM, Yang, Rong R wrote:
> Hi,
> 
> I am developing the HSW’s OCL driver in the linux. I encounter a LRI
> problem on HSW.
> 
> 
> Some gpgpu's applications, which use the shared local memory, must load
> the L3CTRLREG2 and L3CTRLREG3 registers to allocate the SLM in the L3
> cache.
> 
> So I add L3CTRLREG2 and L3CTRLREG3 to the gen7_render_regs to pass the
> cmds parse when exec buffer. But it still don’t work.
> 
> I notice that, on HSW, the commands that load the register, such as
> MI_LOAD_REGISTER_IMM, will be converted to NOOP by the GPU if the batch
> buffer's MI_BATCH_NON_SECURE_HSW bit is set. And after parse cmd, the
> MI_BATCH_NON_SECURE_HSW still set in the kernel. So HSW don’t accept
> LRI commands.
> 
> 
> Can I load these registers in the user space? Or should I hack the
> kernel?
> 
> 
> Yang Rong

I've been asking the kernel developers for the ability to LRI/LRM from
userspace batches for around 1.5 years.  Unfortunately, we're still
waiting, and I honestly have no idea when they're going to finish it.

In the meantime, you can apply the attached patch to your kernel tree to
disable the hardware scanner, letting you run whatever commands you
want.  Obviously, we can't ship this on production systems, but it will
allow you to do your development without having to wait for the kernel team.

--Ken
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