[Intel-gfx] [PATCH 04/71] drm/i915/chv: Flush caches when programming page tables

[Daniel Vetter]

On Wed, Apr 09, 2014 at 01:28:02PM +0300, ville.syrjala at linux.intel.com wrote:
> From: Rafael Barbalho <rafael.barbalho at intel.com>
> 
> Page table updates were getting stuck in the CPU cache on chv causing
> spurious page faults and strange behaviour.
> 
> Signed-off-by: Rafael Barbalho <rafael.barbalho at intel.com>
> [vsyrjala: Add !HAS_LLC checks]
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Reviewed this myself. Poke for the gen7/byt version of this ...
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 3e4d1f0..ba51901 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -267,6 +267,8 @@ static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
>  			num_entries--;
>  		}
>  
> +		if (!HAS_LLC(ppgtt->base.dev))
> +			drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
>  		kunmap_atomic(pt_vaddr);
>  
>  		pte = 0;
> @@ -303,6 +305,8 @@ static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
>  			gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
>  					cache_level, true);
>  		if (++pte == GEN8_PTES_PER_PAGE) {
> +			if (!HAS_LLC(ppgtt->base.dev))
> +				drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
>  			kunmap_atomic(pt_vaddr);
>  			pt_vaddr = NULL;
>  			if (++pde == GEN8_PDES_PER_PAGE) {
> @@ -312,8 +316,11 @@ static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
>  			pte = 0;
>  		}
>  	}
> -	if (pt_vaddr)
> +	if (pt_vaddr) {
> +		if (!HAS_LLC(ppgtt->base.dev))
> +			drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
>  		kunmap_atomic(pt_vaddr);
> +	}
>  }
>  
>  static void gen8_free_page_tables(struct page **pt_pages)
> @@ -576,6 +583,8 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
>  			pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
>  						      I915_CACHE_LLC);
>  		}
> +		if (!HAS_LLC(ppgtt->base.dev))
> +			drm_clflush_virt_range(pd_vaddr, PAGE_SIZE);
>  		kunmap_atomic(pd_vaddr);
>  	}
>  
> -- 
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch