[Intel-gfx] [PATCH 13/50] drm/i915: s/write_tail/submit

[oscar.mateo at intel.com]

From: Oscar Mateo <oscar.mateo at intel.com>

In Execlists we don't really write to the tail register to submit
a workload to the GPU, so the name is going to stop being accurate
soon.

Change and name suggested by Brad.

Cc: Brad Volkin <bradley.d.volkin at intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo at intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 18 +++++++++---------
 drivers/gpu/drm/i915/intel_ringbuffer.h |  4 ++--
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index f18bfb2..6225123 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -63,7 +63,7 @@ void intel_ringbuffer_advance_and_submit(struct intel_engine *ring,
 	if (intel_ring_stopped(ring))
 		return;
 
-	ring->write_tail(ring, ctx, ringbuf->tail);
+	ring->submit(ring, ctx, ringbuf->tail);
 }
 
 static int
@@ -471,7 +471,7 @@ static bool stop_ring(struct intel_engine *ring)
 
 	I915_WRITE_CTL(ring, 0);
 	I915_WRITE_HEAD(ring, 0);
-	ring->write_tail(ring, ring->default_context, 0);
+	ring->submit(ring, ring->default_context, 0);
 
 	if (!IS_GEN2(ring->dev)) {
 		(void)I915_READ_CTL(ring);
@@ -2017,7 +2017,7 @@ int intel_init_render_ring(struct drm_device *dev)
 		}
 		ring->irq_enable_mask = I915_USER_INTERRUPT;
 	}
-	ring->write_tail = ring_write_tail;
+	ring->submit = ring_write_tail;
 	if (IS_HASWELL(dev))
 		ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
 	else if (IS_GEN8(dev))
@@ -2088,7 +2088,7 @@ int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
 		ring->irq_put = i9xx_ring_put_irq;
 	}
 	ring->irq_enable_mask = I915_USER_INTERRUPT;
-	ring->write_tail = ring_write_tail;
+	ring->submit = ring_write_tail;
 	if (INTEL_INFO(dev)->gen >= 4)
 		ring->dispatch_execbuffer = i965_dispatch_execbuffer;
 	else if (IS_I830(dev) || IS_845G(dev))
@@ -2127,11 +2127,11 @@ int intel_init_bsd_ring(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_engine *ring = &dev_priv->ring[VCS];
 
-	ring->write_tail = ring_write_tail;
+	ring->submit = ring_write_tail;
 	if (INTEL_INFO(dev)->gen >= 6) {
 		/* gen6 bsd needs a special wa for tail updates */
 		if (IS_GEN6(dev))
-			ring->write_tail = gen6_bsd_ring_write_tail;
+			ring->submit = gen6_bsd_ring_write_tail;
 		ring->flush = gen6_bsd_ring_flush;
 		ring->add_request = gen6_add_request;
 		ring->get_seqno = gen6_ring_get_seqno;
@@ -2203,7 +2203,7 @@ int intel_init_bsd2_ring(struct drm_device *dev)
 		return -EINVAL;
 	}
 
-	ring->write_tail = ring_write_tail;
+	ring->submit = ring_write_tail;
 	ring->flush = gen6_bsd_ring_flush;
 	ring->add_request = gen6_add_request;
 	ring->get_seqno = gen6_ring_get_seqno;
@@ -2242,7 +2242,7 @@ int intel_init_blt_ring(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_engine *ring = &dev_priv->ring[BCS];
 
-	ring->write_tail = ring_write_tail;
+	ring->submit = ring_write_tail;
 	ring->flush = gen6_ring_flush;
 	ring->add_request = gen6_add_request;
 	ring->get_seqno = gen6_ring_get_seqno;
@@ -2287,7 +2287,7 @@ int intel_init_vebox_ring(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_engine *ring = &dev_priv->ring[VECS];
 
-	ring->write_tail = ring_write_tail;
+	ring->submit = ring_write_tail;
 	ring->flush = gen6_ring_flush;
 	ring->add_request = gen6_add_request;
 	ring->get_seqno = gen6_ring_get_seqno;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index dd85a2b..c224fdc 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -102,8 +102,8 @@ struct intel_engine {
 
 	int		(*init)(struct intel_engine *ring);
 
-	void		(*write_tail)(struct intel_engine *ring,
-				      struct i915_hw_context *ctx, u32 value);
+	void		(*submit)(struct intel_engine *ring,
+				    struct i915_hw_context *ctx, u32 value);
 	int __must_check (*flush)(struct intel_engine *ring,
 				  struct i915_hw_context *ctx,
 				  u32	invalidate_domains,
-- 
1.9.0