[Intel-gfx] [PATCH 35/50] drm/i915/bdw: Add forcewake lock around ELSP writes
oscar.mateo at intel.com
oscar.mateo at intel.com
Fri May 9 14:09:05 CEST 2014
From: Thomas Daniel <thomas.daniel at intel.com>
BSPEC says: SW must set Force Wakeup bit to prevent GT from
entering C6 while ELSP writes are in progress.
Signed-off-by: Thomas Daniel <thomas.daniel at intel.com>
Acked-by: Oscar Mateo <oscar.mateo at intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_lrc.c | 15 +++++++++++----
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 208a4bd..6b39fed 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2694,6 +2694,7 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
+#define I915_RAW_WRITE(reg, val) writel(val, dev_priv->regs + reg)
#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 2eb1c28..54cbb4b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -141,14 +141,21 @@ static void submit_execlist(struct intel_engine *ring,
desc[3] = (u32)(temp >> 32);
desc[2] = (u32)temp;
- I915_WRITE(RING_ELSP(ring), desc[1]);
- I915_WRITE(RING_ELSP(ring), desc[0]);
- I915_WRITE(RING_ELSP(ring), desc[3]);
+ /* Set Force Wakeup bit to prevent GT from entering C6 while
+ * ELSP writes are in progress */
+ gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+
+ I915_RAW_WRITE(RING_ELSP(ring), desc[1]);
+ I915_RAW_WRITE(RING_ELSP(ring), desc[0]);
+ I915_RAW_WRITE(RING_ELSP(ring), desc[3]);
/* The context is automatically loaded after the following */
- I915_WRITE(RING_ELSP(ring), desc[2]);
+ I915_RAW_WRITE(RING_ELSP(ring), desc[2]);
/* ELSP is a write only register, so this serves as a posting read */
POSTING_READ(RING_EXECLIST_STATUS(ring));
+
+ /* Release Force Wakeup */
+ gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
}
static int gen8_switch_context(struct intel_engine *ring,
--
1.9.0
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