[Intel-gfx] [PATCH 05/56] drm/i915: Make pin global flags explicit
Ben Widawsky
benjamin.widawsky at intel.com
Sat May 10 05:59:00 CEST 2014
The driver currently lets callers pin global, and then tries to do
things correctly inside the function. Doing so has two downsides:
1. It's not possible to exclusively pin to a global, or an aliasing
address space.
2. It's difficult to read, and understand.
The eventual goal when realized should fix both of the issues. This patch
which should have no functional impact begins to address these issues
without intentionally breaking things.
v2: Replace PIN_GLOBAL with PIN_ALIASING in _pin(). Copy paste error
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
---
drivers/gpu/drm/i915/i915_drv.h | 4 +++-
drivers/gpu/drm/i915/i915_gem.c | 31 +++++++++++++++++++++++-------
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 8 ++++++--
drivers/gpu/drm/i915/i915_gem_gtt.c | 12 ++++++++++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 4 ++++
5 files changed, 47 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 88d3d82..62e1ecb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2136,6 +2136,8 @@ void i915_gem_vma_destroy(struct i915_vma *vma);
#define PIN_MAPPABLE 0x1
#define PIN_NONBLOCK 0x2
#define PIN_GLOBAL 0x4
+#define PIN_ALIASING 0x8
+#define PIN_GLOBAL_ALIASED (PIN_ALIASING | PIN_GLOBAL)
int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
struct i915_address_space *vm,
uint32_t alignment,
@@ -2362,7 +2364,7 @@ i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
uint32_t alignment,
unsigned flags)
{
- return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, flags | PIN_GLOBAL);
+ return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, flags | PIN_GLOBAL_ALIASED);
}
static inline int
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 59b0e67..e3ac643 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3231,8 +3231,12 @@ i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
size_t gtt_max =
flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
struct i915_vma *vma;
+ u32 vma_bind_flags = 0;
int ret;
+ if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
+ flags |= PIN_GLOBAL;
+
fence_size = i915_gem_get_gtt_size(dev,
obj->base.size,
obj->tiling_mode);
@@ -3316,9 +3320,11 @@ search_free:
WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
+ if (flags & PIN_GLOBAL_ALIASED)
+ vma_bind_flags = GLOBAL_BIND | ALIASING_BIND;
+
trace_i915_vma_bind(vma, flags);
- i915_gem_vma_bind(vma, obj->cache_level,
- flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0);
+ i915_gem_vma_bind(vma, obj->cache_level, vma_bind_flags);
i915_gem_verify_gtt(dev);
return vma;
@@ -3521,9 +3527,14 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
}
list_for_each_entry(vma, &obj->vma_list, vma_link)
- if (drm_mm_node_allocated(&vma->node))
- i915_gem_vma_bind(vma, cache_level,
- obj->has_global_gtt_mapping ? GLOBAL_BIND : 0);
+ if (drm_mm_node_allocated(&vma->node)) {
+ u32 bind_flags = 0;
+ if (obj->has_global_gtt_mapping)
+ bind_flags |= GLOBAL_BIND;
+ if (obj->has_aliasing_ppgtt_mapping)
+ bind_flags |= ALIASING_BIND;
+ i915_gem_vma_bind(vma, cache_level, bind_flags);
+ }
}
list_for_each_entry(vma, &obj->vma_list, vma_link)
@@ -3891,8 +3902,14 @@ i915_gem_object_pin(struct drm_i915_gem_object *obj,
return PTR_ERR(vma);
}
- if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping)
- i915_gem_vma_bind(vma, obj->cache_level, GLOBAL_BIND);
+ if (flags & PIN_GLOBAL_ALIASED) {
+ u32 bind_flags = 0;
+ if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping)
+ bind_flags |= GLOBAL_BIND;
+ if (flags & PIN_ALIASING && !obj->has_aliasing_ppgtt_mapping)
+ bind_flags |= ALIASING_BIND;
+ i915_gem_vma_bind(vma, obj->cache_level, bind_flags);
+ }
vma->pin_count++;
if (flags & PIN_MAPPABLE)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index cd9b932..7cad10f 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -374,7 +374,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
list_first_entry(&target_i915_obj->vma_list,
typeof(*vma), vma_link);
i915_gem_vma_bind(vma, target_i915_obj->cache_level,
- GLOBAL_BIND);
+ GLOBAL_BIND | ALIASING_BIND);
}
/* Validate that the target is in a valid r/w GPU domain */
@@ -561,6 +561,7 @@ i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
if (need_fence || need_reloc_mappable(vma))
flags |= PIN_MAPPABLE;
+ /* FIXME: What kind of bind does Chris want? */
if (entry->flags & EXEC_OBJECT_NEEDS_GTT)
flags |= PIN_GLOBAL;
@@ -1270,7 +1271,10 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
* allocate space first */
struct i915_vma *vma = i915_gem_obj_to_ggtt(batch_obj);
BUG_ON(!vma);
- i915_gem_vma_bind(vma, batch_obj->cache_level, GLOBAL_BIND);
+ /* FIXME: Current secure dispatch code actually uses PPGTT. We
+ * need to fix this eventually */
+ i915_gem_vma_bind(vma, batch_obj->cache_level,
+ GLOBAL_BIND | ALIASING_BIND);
}
if (flags & I915_DISPATCH_SECURE)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 87d92d0..226afea 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1339,8 +1339,16 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
* Unfortunately above, we've just wiped out the mappings
* without telling our object about it. So we need to fake it.
*/
- obj->has_global_gtt_mapping = 0;
- i915_gem_vma_bind(vma, obj->cache_level, GLOBAL_BIND);
+ if (obj->has_global_gtt_mapping || obj->has_aliasing_ppgtt_mapping) {
+ u32 bind_flags = 0;
+ if (obj->has_global_gtt_mapping)
+ bind_flags |= GLOBAL_BIND;
+ if (obj->has_aliasing_ppgtt_mapping)
+ bind_flags |= ALIASING_BIND;
+ obj->has_global_gtt_mapping = 0;
+ obj->has_aliasing_ppgtt_mapping = 0;
+ i915_gem_vma_bind(vma, obj->cache_level, bind_flags);
+ }
}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index cfca023..5635c65 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -153,7 +153,11 @@ struct i915_vma {
* setting the valid PTE entries to a reserved scratch page. */
void (*unbind_vma)(struct i915_vma *vma);
/* Map an object into an address space with the given cache flags. */
+
+/* Only use this if you know you want a strictly global binding */
#define GLOBAL_BIND (1<<0)
+/* Only use this if you know you want a strictly aliased binding */
+#define ALIASING_BIND (1<<1)
void (*bind_vma)(struct i915_vma *vma,
enum i915_cache_level cache_level,
u32 flags);
--
1.9.2
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