[Intel-gfx] [PATCH 17/71] drm/i915/chv: Update Cherryview DPLL changes to support Port D. v2

[Imre Deak]

On Wed, 2014-04-09 at 13:28 +0300, ville.syrjala at linux.intel.com wrote:
> From: Chon Ming Lee <chon.ming.lee at intel.com>
> 
> The additional DPLL registers added to support Port D.  Besides, add
> some new PHY control and status registers based on B-spec.
> 
> v2: Based on Ville review
> 	- Corrected DPIO_PHY_STATUS offset and name.
>     - Rebase based on upstream change after introduce enum dpio_phy and
>       enum dpio_channel.
> 
> v3: Rebased on top of Antti's 3-pipe prep patch. Note that the new offsets for
> the DPLL registers aren't in place yet, so this introduces a slight regression.
> But since 3 pipe support isn't fully enabled yet anyaway in -internal this
> shouldn't matter too much.
> 
> Signed-off-by: Chon Ming Lee <chon.ming.lee at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |  6 ++++++
>  drivers/gpu/drm/i915/intel_display.c | 11 +++++++++--
>  drivers/gpu/drm/i915/intel_drv.h     |  1 +
>  3 files changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index beb04ab..8aea092 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -29,6 +29,8 @@
>  #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
>  
>  #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
> +#define _PIPE3(pipe, a, b, c) (pipe < 2 ? _PIPE(pipe, a, b) : c)
> +#define _PORT3(port, a, b, c) (port < 2 ? _PORT(port, a, b) : c)

These could go to patch 71, where they're first used. Either way:
Reviewed-by: Imre Deak <imre.deak at intel.com>

>  
>  #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
>  #define _MASKED_BIT_DISABLE(a) ((a) << 16)
> @@ -1385,6 +1387,10 @@ enum punit_power_well {
>  #define   DPLL_PORTB_READY_MASK		(0xf)
>  
>  #define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
> +
> +/* Additional CHV pll/phy registers */
> +#define DPIO_PHY_STATUS			(VLV_DISPLAY_BASE + 0x6240)
> +#define   DPLL_PORTD_READY_MASK		(0xf)
>  /*
>   * The i830 generation, in LVDS mode, defines P1 as the bit number set within
>   * this field (only one bit may be set).
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index df6732e..153f244 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1535,21 +1535,28 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
>  		struct intel_digital_port *dport)
>  {
>  	u32 port_mask;
> +	int dpll_reg;
>  
>  	switch (dport->port) {
>  	case PORT_B:
>  		port_mask = DPLL_PORTB_READY_MASK;
> +		dpll_reg = DPLL(0);
>  		break;
>  	case PORT_C:
>  		port_mask = DPLL_PORTC_READY_MASK;
> +		dpll_reg = DPLL(0);
> +		break;
> +	case PORT_D:
> +		port_mask = DPLL_PORTD_READY_MASK;
> +		dpll_reg = DPIO_PHY_STATUS;
>  		break;
>  	default:
>  		BUG();
>  	}
>  
> -	if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
> +	if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
>  		WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
> -		     port_name(dport->port), I915_READ(DPLL(0)));
> +		     port_name(dport->port), I915_READ(dpll_reg));
>  }
>  
>  /**
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 9002e77..087e471 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -535,6 +535,7 @@ vlv_dport_to_channel(struct intel_digital_port *dport)
>  {
>  	switch (dport->port) {
>  	case PORT_B:
> +	case PORT_D:
>  		return DPIO_CH0;
>  	case PORT_C:
>  		return DPIO_CH1;

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