[Intel-gfx] [PATCH 49.1/50] drm/i915/bdw: Do not call intel_runtime_pm_get() in an interrupt

[oscar.mateo at intel.com]

From: Oscar Mateo <oscar.mateo at intel.com>

Or with a spinlock grabbed, because it might sleep, which is not
a nice thing to do. Instead, do the runtime_pm get/put together
with the create/destroy request, and handle the forcewake get/put
directly.

This can be squashed with:

[PATCH 35/50] drm/i915/bdw: Add forcewake lock around ELSP writes

but it needs some patch reordering, so I will leave it for the next
patchset version.

Signed-off-by: Oscar Mateo <oscar.mateo at intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 26 +++++++++++++++++++++-----
 1 file changed, 21 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index e624580..55255e8 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -205,6 +205,7 @@ static void submit_execlist(struct intel_engine *ring,
 	struct drm_i915_private *dev_priv = ring->dev->dev_private;
 	uint64_t temp = 0;
 	uint32_t desc[4];
+	unsigned long flags;
 
 	/* XXX: You must always write both descriptors in the order below. */
 	if (ctx_obj1)
@@ -218,9 +219,17 @@ static void submit_execlist(struct intel_engine *ring,
 	desc[3] = (u32)(temp >> 32);
 	desc[2] = (u32)temp;
 
-	/* Set Force Wakeup bit to prevent GT from entering C6 while
-	 * ELSP writes are in progress */
-	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+	/* Set Force Wakeup bit to prevent GT from entering C6 while ELSP writes
+	 * are in progress.
+	 *
+	 * The other problem is that we can't just call gen6_gt_force_wake_get()
+	 * because that function calls intel_runtime_pm_get(), which might sleep.
+	 * Instead, we do the runtime_pm_get/put when creating/destroying requests.
+	 */
+	spin_lock_irqsave(&dev_priv->uncore.lock, flags);
+	if (dev_priv->uncore.forcewake_count++ == 0)
+		dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
+	spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
 
 	I915_RAW_WRITE(RING_ELSP(ring), desc[1]);
 	I915_RAW_WRITE(RING_ELSP(ring), desc[0]);
@@ -231,8 +240,11 @@ static void submit_execlist(struct intel_engine *ring,
 	/* ELSP is a write only register, so this serves as a posting read */
 	POSTING_READ(RING_EXECLIST_STATUS(ring));
 
-	/* Release Force Wakeup */
-	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
+	/* Release Force Wakeup (see the big comment above). */
+	spin_lock_irqsave(&dev_priv->uncore.lock, flags);
+	if (--dev_priv->uncore.forcewake_count == 0)
+		dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
+	spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
 }
 
 static int lr_context_write_tail(struct drm_i915_gem_object *ctx_obj, u32 tail)
@@ -398,6 +410,9 @@ static void free_request_task(struct work_struct *work)
 	struct drm_i915_gem_request *req =
 			container_of(work, struct drm_i915_gem_request, work);
 	struct drm_device *dev = req->ring->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	intel_runtime_pm_put(dev_priv);
 
 	mutex_lock(&dev->struct_mutex);
 	i915_gem_context_unreference(req->ctx);
@@ -424,6 +439,7 @@ int gen8_switch_context_queue(struct intel_engine *ring,
 	i915_gem_context_reference(req->ctx);
 	req->tail = tail;
 	INIT_WORK(&req->work, free_request_task);
+	intel_runtime_pm_get(dev_priv);
 
 	spin_lock_irqsave(&ring->execlist_lock, flags);
 
-- 
1.9.0