[Intel-gfx] [PATCH] drm/i915: prevent gt fifo count underflow

[Mika Kuoppala]

If we get the final value of zero as a count of free
entries available, we will underflow our own fifo_count
and then it will take a long time before we check things again.
Admittedly we are in trouble already if we get into this situation,
but prevent the underflow by checking against zero before decreasing
fifo_count.

Signed-off-by: Mika Kuoppala <mika.kuoppala at intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 76dc185..159f8ab 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -174,7 +174,7 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 		}
 		if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 			++ret;
-		dev_priv->uncore.fifo_count = fifo;
+		dev_priv->uncore.fifo_count = fifo ?: 1;
 	}
 	dev_priv->uncore.fifo_count--;
 
-- 
1.7.9.5