[Intel-gfx] [PATCH 7/9] drm/i915: Improve gen3/4 frame counter

[akash goel]

Reviewed the patch & it looks fine.

Reviewed-by: "Akash Goel <akash.goels at gmail.com>"
On Tue, Apr 29, 2014 at 4:05 PM, <ville.syrjala at linux.intel.com> wrote:

> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> Currently the logic to fix up the frame counter on gen3/4 assumes that
> start of vblank occurs at vblank_start*htotal pixels, when in fact
> it occurs htotal-hsync_start pixels earlier. Apply the appropriate
> adjustment to make the frame counter more accurate.
>
> Also fix the vblank start position for interlaced display modes.
>
> Reviewed-by: Imre Deak <imre.deak at intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 21 ++++++++++++++++-----
>  1 file changed, 16 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index 64cd888..742f276 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -683,7 +683,7 @@ static u32 i915_get_vblank_counter(struct drm_device
> *dev, int pipe)
>         struct drm_i915_private *dev_priv = dev->dev_private;
>         unsigned long high_frame;
>         unsigned long low_frame;
> -       u32 high1, high2, low, pixel, vbl_start;
> +       u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
>
>         if (!i915_pipe_enabled(dev, pipe)) {
>                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
> @@ -697,17 +697,28 @@ static u32 i915_get_vblank_counter(struct drm_device
> *dev, int pipe)
>                 const struct drm_display_mode *mode =
>                         &intel_crtc->config.adjusted_mode;
>
> -               vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
> +               htotal = mode->crtc_htotal;
> +               hsync_start = mode->crtc_hsync_start;
> +               vbl_start = mode->crtc_vblank_start;
> +               if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> +                       vbl_start = DIV_ROUND_UP(vbl_start, 2);
>         } else {
>                 enum transcoder cpu_transcoder = (enum transcoder) pipe;
> -               u32 htotal;
>
>                 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) &
> 0x1fff) + 1;
> +               hsync_start = (I915_READ(HSYNC(cpu_transcoder))  & 0x1fff)
> + 1;
>                 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) +
> 1;
> -
> -               vbl_start *= htotal;
> +               if ((I915_READ(PIPECONF(cpu_transcoder)) &
> +                    PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE)
> +                       vbl_start = DIV_ROUND_UP(vbl_start, 2);
>         }
>
> +       /* Convert to pixel count */
> +       vbl_start *= htotal;
> +
> +       /* Start of vblank event occurs at start of hsync */
> +       vbl_start -= htotal - hsync_start;
> +
>         high_frame = PIPEFRAME(pipe);
>         low_frame = PIPEFRAMEPIXEL(pipe);
>
> --
> 1.8.3.2
>
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