[Intel-gfx] [PATCH 1/2] drm/i915: rename IOSF sideband opcodes according to the spec
Jesse Barnes
jbarnes at virtuousgeek.org
Mon May 19 17:00:08 CEST 2014
On Mon, 19 May 2014 11:41:17 +0300
Imre Deak <imre.deak at intel.com> wrote:
> These opcodes are not specific for an endpoint, but are the same for all
> endpoints. So rename them accordingly, using the name the VLV2 sideband
> HAS uses. Also move the macros to the .c file, since they aren't used
> anywhere else.
>
> Signed-off-by: Imre Deak <imre.deak at intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 ----
> drivers/gpu/drm/i915/intel_sideband.c | 51 ++++++++++++++++++++---------------
> 2 files changed, 30 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ac90786..3d437d1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -484,9 +484,6 @@
> /* See configdb bunit SB addr map */
> #define BUNIT_REG_BISOC 0x11
>
> -#define PUNIT_OPCODE_REG_READ 6
> -#define PUNIT_OPCODE_REG_WRITE 7
> -
> #define PUNIT_REG_DSPFREQ 0x36
> #define DSPFREQSTAT_SHIFT 30
> #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
> @@ -580,8 +577,6 @@ enum punit_power_well {
> * Note: digital port B is DDI0, digital pot C is DDI1
> */
> #define DPIO_DEVFN 0
> -#define DPIO_OPCODE_REG_WRITE 1
> -#define DPIO_OPCODE_REG_READ 0
>
> #define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110)
> #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index b1a5514..f3909d5 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -29,12 +29,21 @@
> * IOSF sideband, see VLV2_SidebandMsg_HAS.docx and
> * VLV_VLV2_PUNIT_HAS_0.8.docx
> */
> +
> +/* Standard MMIO read, non-posted */
> +#define SB_MRD_NP 0x00
> +/* Standard MMIO write, non-posted */
> +#define SB_MWR_NP 0x01
> +/* Private register read, double-word addressing, non-posted */
> +#define SB_CRRDDA_NP 0x06
> +/* Private register write, double-word addressing, non-posted */
> +#define SB_CRWRDA_NP 0x07
> +
> static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
> u32 port, u32 opcode, u32 addr, u32 *val)
> {
> u32 cmd, be = 0xf, bar = 0;
> - bool is_read = (opcode == PUNIT_OPCODE_REG_READ ||
> - opcode == DPIO_OPCODE_REG_READ);
> + bool is_read = (opcode == SB_MRD_NP || opcode == SB_CRRDDA_NP);
>
> cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
> (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
> @@ -74,7 +83,7 @@ u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr)
>
> mutex_lock(&dev_priv->dpio_lock);
> vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
> - PUNIT_OPCODE_REG_READ, addr, &val);
> + SB_CRRDDA_NP, addr, &val);
> mutex_unlock(&dev_priv->dpio_lock);
>
> return val;
> @@ -86,7 +95,7 @@ void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
>
> mutex_lock(&dev_priv->dpio_lock);
> vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
> - PUNIT_OPCODE_REG_WRITE, addr, &val);
> + SB_CRWRDA_NP, addr, &val);
> mutex_unlock(&dev_priv->dpio_lock);
> }
>
> @@ -95,7 +104,7 @@ u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg)
> u32 val = 0;
>
> vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT,
> - PUNIT_OPCODE_REG_READ, reg, &val);
> + SB_CRRDDA_NP, reg, &val);
>
> return val;
> }
> @@ -103,7 +112,7 @@ u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg)
> void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
> {
> vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT,
> - PUNIT_OPCODE_REG_WRITE, reg, &val);
> + SB_CRWRDA_NP, reg, &val);
> }
>
> u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
> @@ -114,7 +123,7 @@ u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
>
> mutex_lock(&dev_priv->dpio_lock);
> vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_NC,
> - PUNIT_OPCODE_REG_READ, addr, &val);
> + SB_CRRDDA_NP, addr, &val);
> mutex_unlock(&dev_priv->dpio_lock);
>
> return val;
> @@ -124,56 +133,56 @@ u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg)
> {
> u32 val = 0;
> vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC,
> - PUNIT_OPCODE_REG_READ, reg, &val);
> + SB_CRRDDA_NP, reg, &val);
> return val;
> }
>
> void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
> {
> vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC,
> - PUNIT_OPCODE_REG_WRITE, reg, &val);
> + SB_CRWRDA_NP, reg, &val);
> }
>
> u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg)
> {
> u32 val = 0;
> vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK,
> - PUNIT_OPCODE_REG_READ, reg, &val);
> + SB_CRRDDA_NP, reg, &val);
> return val;
> }
>
> void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
> {
> vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK,
> - PUNIT_OPCODE_REG_WRITE, reg, &val);
> + SB_CRWRDA_NP, reg, &val);
> }
>
> u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg)
> {
> u32 val = 0;
> vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU,
> - PUNIT_OPCODE_REG_READ, reg, &val);
> + SB_CRRDDA_NP, reg, &val);
> return val;
> }
>
> void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
> {
> vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU,
> - PUNIT_OPCODE_REG_WRITE, reg, &val);
> + SB_CRWRDA_NP, reg, &val);
> }
>
> u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg)
> {
> u32 val = 0;
> vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE,
> - PUNIT_OPCODE_REG_READ, reg, &val);
> + SB_CRRDDA_NP, reg, &val);
> return val;
> }
>
> void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
> {
> vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE,
> - PUNIT_OPCODE_REG_WRITE, reg, &val);
> + SB_CRWRDA_NP, reg, &val);
> }
>
> u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
> @@ -181,7 +190,7 @@ u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
> u32 val = 0;
>
> vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
> - DPIO_OPCODE_REG_READ, reg, &val);
> + SB_MRD_NP, reg, &val);
>
> /*
> * FIXME: There might be some registers where all 1's is a valid value,
> @@ -196,7 +205,7 @@ u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
> void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val)
> {
> vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
> - DPIO_OPCODE_REG_WRITE, reg, &val);
> + SB_MWR_NP, reg, &val);
> }
>
> /* SBI access */
> @@ -261,13 +270,13 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
> u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
> {
> u32 val = 0;
> - vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI,
> - DPIO_OPCODE_REG_READ, reg, &val);
> + vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MRD_NP,
> + reg, &val);
> return val;
> }
>
> void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
> {
> - vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI,
> - DPIO_OPCODE_REG_WRITE, reg, &val);
> + vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MWR_NP,
> + reg, &val);
> }
Reviewed-by: Jesse Barnes <jbarnes at virtuousgeek.org>
--
Jesse Barnes, Intel Open Source Technology Center
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