[Intel-gfx] [PATCH 2/2] drm/i915: vlv/chv: fix DSI sideband register accessing

[Imre Deak]

On Mon, 2014-05-19 at 08:01 -0700, Jesse Barnes wrote:
> On Mon, 19 May 2014 11:41:18 +0300
> Imre Deak <imre.deak at intel.com> wrote:
> 
> > So far we used the wrong opcodes to access the DSI registers, so the
> > register writes during DSI programming didn't actually succeed and left
> > the registers unchanged. This wasn't a problem for the initial modeset,
> > where the BIOS-programmed values happened to work, but after resuming
> > from s0ix these registers are reset and failing to program them results
> > in a blank screen.
> > 
> > Signed-off-by: Imre Deak <imre.deak at intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_sideband.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> > index f3909d5..01d841e 100644
> > --- a/drivers/gpu/drm/i915/intel_sideband.c
> > +++ b/drivers/gpu/drm/i915/intel_sideband.c
> > @@ -270,13 +270,13 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
> >  u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
> >  {
> >  	u32 val = 0;
> > -	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MRD_NP,
> > +	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
> >  			reg, &val);
> >  	return val;
> >  }
> >  
> >  void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
> >  {
> > -	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MWR_NP,
> > +	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
> >  			reg, &val);
> >  }
> 
> Nice find... is this documented somewhere so we can put a reference
> in?  Or is it in the Punit HAS somewhere already and we just missed it?

I found it in the VLV2_SidebandMsg_HAS, there is already a comment in
this file with a reference to it.

--Imre

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