[Intel-gfx] [PATCH 43/71] drm/i915/chv: Add a bunch of pre production workarounds

[Damien Lespiau]

On Wed, Apr 09, 2014 at 01:28:41PM +0300, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> The following workarounds should be needed for pre-production hardware
> only:
> * WaDisablePwrmtrEvent:chv
> * WaSetMaskForGfxBusyness:chv
> * WaDisableGunitClockGating:chv
> * WaDisableFfDopClockGating:chv
> * WaDisableDopClockGating:chv
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

What about that hunk?

> +	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> +		   GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);

I couldn't find a W/A in the db nor in BSpec. The rest looks good
though.

-- 
Damien

> ---
>  drivers/gpu/drm/i915/i915_reg.h |  3 +++
>  drivers/gpu/drm/i915/intel_pm.c | 20 +++++++++++++++++++-
>  2 files changed, 22 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ac5047b..7587752 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1024,6 +1024,7 @@ enum punit_power_well {
>  #define IMR		0x020a8
>  #define ISR		0x020ac
>  #define VLV_GUNIT_CLOCK_GATE	(VLV_DISPLAY_BASE + 0x2060)
> +#define   GINT_DIS		(1<<22)
>  #define   GCFG_DIS		(1<<8)
>  #define VLV_IIR_RW	(VLV_DISPLAY_BASE + 0x2084)
>  #define VLV_IER		(VLV_DISPLAY_BASE + 0x20a0)
> @@ -1154,6 +1155,7 @@ enum punit_power_well {
>  
>  #define GEN6_RC_SLEEP_PSMI_CONTROL	0x2050
>  #define   GEN8_RC_SEMA_IDLE_MSG_DISABLE	(1 << 12)
> +#define   GEN8_FF_DOP_CLOCK_GATE_DISABLE	(1<<10)
>  
>  #define GEN6_BSD_SLEEP_PSMI_CONTROL	0x12050
>  #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
> @@ -5186,6 +5188,7 @@ enum punit_power_well {
>  #define  HSW_EDRAM_PRESENT			0x120010
>  
>  #define GEN6_UCGCTL1				0x9400
> +# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE		(1 << 16)
>  # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE		(1 << 5)
>  # define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 60f876c..587d32f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3775,10 +3775,14 @@ static void cherryview_enable_rps(struct drm_device *dev)
>  
>  	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
>  
> +	/* WaDisablePwrmtrEvent:chv (pre-production hw) */
> +	I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
> +	I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
> +
>  	/* 5: Enable RPS */
>  	I915_WRITE(GEN6_RP_CONTROL,
>  		   GEN6_RP_MEDIA_HW_NORMAL_MODE |
> -		   GEN6_RP_MEDIA_IS_GFX |
> +		   GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
>  		   GEN6_RP_ENABLE |
>  		   GEN6_RP_UP_BUSY_AVG |
>  		   GEN6_RP_DOWN_IDLE_AVG);
> @@ -5409,6 +5413,20 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
>  	/* WaDisableSamplerPowerBypass:chv (pre-production hw) */
>  	I915_WRITE(HALF_SLICE_CHICKEN3,
>  		   _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
> +
> +	/* WaDisableGunitClockGating:chv (pre-production hw) */
> +	I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
> +		   GINT_DIS);
> +
> +	/* WaDisableFfDopClockGating:chv (pre-production hw) */
> +	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
> +		   _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
> +
> +	/* WaDisableDopClockGating:chv (pre-production hw) */
> +	I915_WRITE(GEN7_ROW_CHICKEN2,
> +		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> +	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> +		   GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
>  }
>  
>  static void g4x_init_clock_gating(struct drm_device *dev)
> -- 
> 1.8.3.2
> 
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