[Intel-gfx] [PATCH 64/71] drm/i915/chv: Don't use PCS group access reads

[Ville Syrjälä]

On Tue, May 20, 2014 at 03:50:02PM +0200, Daniel Vetter wrote:
> On Wed, Apr 09, 2014 at 07:56:50PM +0300, Ville Syrjälä wrote:
> > On Wed, Apr 09, 2014 at 06:18:38PM +0200, Daniel Vetter wrote:
> > > On Wed, Apr 09, 2014 at 01:29:02PM +0300, ville.syrjala at linux.intel.com wrote:
> > > > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > > > 
> > > > All PCS groups access reads return 0xffffffff, so we can't use group
> > > > access for RMW cycles. Instead target each spline separately.
> > > 
> > > I have no idea what PCS means here and spline ... Can you please expand
> > > for those who haven't yet lost their souls in chv docs? Just so we have a
> > > commonly-understood jargon for talking about this stuff.
> > 
> > I guess we should have that somewhere as a comment. The same terminology
> > applies to VLV as well.
> 
> Haven't seen the promised patch yet.

"[PATCH] drm/i915: Add a brief description of the VLV display PHY internals" & co.

-- 
Ville Syrjälä
Intel OTC