[Intel-gfx] [PATCH 3/3] drm/i915: Provide DPIO diagrams as docboox tables

[Daniel Vetter]

On Wed, May 21, 2014 at 06:59:03PM +0800, Lee, Chon Ming wrote:
> On 04/25 20:14, ville.syrjala at linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > 
> > The ascii art version of the DPIO diagram gets mangled by docbook, so
> > we can't use it there. Insted provide another version built using
> > <table>.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> When generating drm.tmpl to html, it say no structured comments found for
> i915_reg.h
> 
> I am getting this error when displaying the link for i915_reg.h in HTML format: 
> Document generation inconsistency.
> 
> Not sure is some issue on my side because I have issue apply this patch series,
> so I apply manually.
> 
> Anyway, the table below is similar to your previous patch.  So,

Worked here, dunno what's broken on your side ... Note that some docbooks
moved around in 3.15-rc1 and the build system doesn't handle that. You
need to run a git clean -dfx in the Documentation directory to fix that.

> Reviewed-by: Chon Ming Lee <chon.ming.lee at intel.com>

Both patches merged, thanks.
-Daniel

> 
> > ---
> >  Documentation/DocBook/drm.tmpl | 86 ++++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 86 insertions(+)
> > 
> > diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
> > index e361ccd..bf11fe5 100644
> > --- a/Documentation/DocBook/drm.tmpl
> > +++ b/Documentation/DocBook/drm.tmpl
> > @@ -2945,6 +2945,92 @@ int num_ioctls;</synopsis>
> >        <sect2>
> >          <title>DPIO</title>
> >  !Pdrivers/gpu/drm/i915/i915_reg.h DPIO
> > +	<table id="dpiox2">
> > +	  <title>Dual channel PHY (VLV/CHV)</title>
> > +	  <tgroup cols="8">
> > +	    <colspec colname="c0" />
> > +	    <colspec colname="c1" />
> > +	    <colspec colname="c2" />
> > +	    <colspec colname="c3" />
> > +	    <colspec colname="c4" />
> > +	    <colspec colname="c5" />
> > +	    <colspec colname="c6" />
> > +	    <colspec colname="c7" />
> > +	    <spanspec spanname="ch0" namest="c0" nameend="c3" />
> > +	    <spanspec spanname="ch1" namest="c4" nameend="c7" />
> > +	    <spanspec spanname="ch0pcs01" namest="c0" nameend="c1" />
> > +	    <spanspec spanname="ch0pcs23" namest="c2" nameend="c3" />
> > +	    <spanspec spanname="ch1pcs01" namest="c4" nameend="c5" />
> > +	    <spanspec spanname="ch1pcs23" namest="c6" nameend="c7" />
> > +	    <thead>
> > +	      <row>
> > +		<entry spanname="ch0">CH0</entry>
> > +		<entry spanname="ch1">CH1</entry>
> > +	      </row>
> > +	    </thead>
> > +	    <tbody valign="top" align="center">
> > +	      <row>
> > +		<entry spanname="ch0">CMN/PLL/REF</entry>
> > +		<entry spanname="ch1">CMN/PLL/REF</entry>
> > +	      </row>
> > +	      <row>
> > +		<entry spanname="ch0pcs01">PCS01</entry>
> > +		<entry spanname="ch0pcs23">PCS23</entry>
> > +		<entry spanname="ch1pcs01">PCS01</entry>
> > +		<entry spanname="ch1pcs23">PCS23</entry>
> > +	      </row>
> > +	      <row>
> > +		<entry>TX0</entry>
> > +		<entry>TX1</entry>
> > +		<entry>TX2</entry>
> > +		<entry>TX3</entry>
> > +		<entry>TX0</entry>
> > +		<entry>TX1</entry>
> > +		<entry>TX2</entry>
> > +		<entry>TX3</entry>
> > +	      </row>
> > +	      <row>
> > +		<entry spanname="ch0">DDI0</entry>
> > +		<entry spanname="ch1">DDI1</entry>
> > +	      </row>
> > +	    </tbody>
> > +	  </tgroup>
> > +	</table>
> > +	<table id="dpiox1">
> > +	  <title>Single channel PHY (CHV)</title>
> > +	  <tgroup cols="4">
> > +	    <colspec colname="c0" />
> > +	    <colspec colname="c1" />
> > +	    <colspec colname="c2" />
> > +	    <colspec colname="c3" />
> > +	    <spanspec spanname="ch0" namest="c0" nameend="c3" />
> > +	    <spanspec spanname="ch0pcs01" namest="c0" nameend="c1" />
> > +	    <spanspec spanname="ch0pcs23" namest="c2" nameend="c3" />
> > +	    <thead>
> > +	      <row>
> > +		<entry spanname="ch0">CH0</entry>
> > +	      </row>
> > +	    </thead>
> > +	    <tbody valign="top" align="center">
> > +	      <row>
> > +		<entry spanname="ch0">CMN/PLL/REF</entry>
> > +	      </row>
> > +	      <row>
> > +		<entry spanname="ch0pcs01">PCS01</entry>
> > +		<entry spanname="ch0pcs23">PCS23</entry>
> > +	      </row>
> > +	      <row>
> > +		<entry>TX0</entry>
> > +		<entry>TX1</entry>
> > +		<entry>TX2</entry>
> > +		<entry>TX3</entry>
> > +	      </row>
> > +	      <row>
> > +		<entry spanname="ch0">DDI2</entry>
> > +	      </row>
> > +	    </tbody>
> > +	  </tgroup>
> > +	</table>
> >        </sect2>
> >      </sect1>
> >  
> > -- 
> > 1.8.3.2
> > 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch