[Intel-gfx] [PATCH 6/6] drm/i915: Implement WaVcpClkGateDisableForMediaReset:ctg, elk

[Daniel Vetter]

On Tue, May 20, 2014 at 11:46:45AM -0700, Jesse Barnes wrote:
> On Mon, 19 May 2014 19:23:27 +0300
> ville.syrjala at linux.intel.com wrote:
> 
> > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > 
> > Apparently we need to disable VCP unit clock gating around media reset
> > on g4x.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h     |  4 ++++
> >  drivers/gpu/drm/i915/intel_uncore.c | 36 +++++++++++++++++++++++++++++++++++-
> >  2 files changed, 39 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 6522af4..543f23c 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1724,6 +1724,10 @@ enum punit_power_well {
> >  #define VF_UNIT_CLOCK_GATE_DISABLE		(1 << 9)
> >  #define GS_UNIT_CLOCK_GATE_DISABLE		(1 << 7)
> >  #define CL_UNIT_CLOCK_GATE_DISABLE		(1 << 6)
> > +
> > +#define VDECCLK_GATE_D		0x620C		/* g4x only */
> > +#define  VCP_UNIT_CLOCK_GATE_DISABLE		(1 << 4)
> > +
> >  #define RAMCLK_GATE_D		0x6210		/* CRL only */
> >  #define DEUC			0x6214          /* CRL only */
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> > index cd0d6e2..67385a9 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -990,6 +990,36 @@ static int i965_do_reset(struct drm_device *dev)
> >  	return 0;
> >  }
> >  
> > +static int g4x_do_reset(struct drm_device *dev)
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	int ret;
> > +
> > +	pci_write_config_byte(dev->pdev, I965_GDRST,
> > +			      GRDOM_RENDER | GRDOM_RESET_ENABLE);
> > +	ret =  wait_for(i965_reset_complete(dev), 500);
> > +	if (ret)
> > +		return ret;
> > +
> > +	/* WaVcpClkGateDisableForMediaReset:ctg,elk */
> > +	I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
> > +	POSTING_READ(VDECCLK_GATE_D);
> > +
> > +	pci_write_config_byte(dev->pdev, I965_GDRST,
> > +			      GRDOM_MEDIA | GRDOM_RESET_ENABLE);
> > +	ret =  wait_for(i965_reset_complete(dev), 500);
> > +	if (ret)
> > +		return ret;
> > +
> > +	/* WaVcpClkGateDisableForMediaReset:ctg,elk */
> > +	I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
> > +	POSTING_READ(VDECCLK_GATE_D);
> > +
> > +	pci_write_config_byte(dev->pdev, I965_GDRST, 0);
> > +
> > +	return 0;
> > +}
> > +
> >  static int ironlake_do_reset(struct drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -1042,7 +1072,11 @@ int intel_gpu_reset(struct drm_device *dev)
> >  	case 7:
> >  	case 6: return gen6_do_reset(dev);
> >  	case 5: return ironlake_do_reset(dev);
> > -	case 4: return i965_do_reset(dev);
> > +	case 4:
> > +		if (IS_G4X(dev))
> > +			return g4x_do_reset(dev);
> > +		else
> > +			return i965_do_reset(dev);
> >  	default: return -ENODEV;
> >  	}
> >  }
> 
> Given how the reset flow stuff works this seems sensible, but I
> couldn't find it in the docs I have.  Shouldn't do any harm at the very
> worst...
> 
> Acked-by: Jesse Barnes <jbarnes at virtuousgeek.org>

I want the g4x/i965 split, so also merged this one here ;-)
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch