[Intel-gfx] [RFC][PATCH] drm/i915: Don't promote UC to WT automagically

[ville.syrjala at linux.intel.com]

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

If the object is already UC leave it as UC instead of automagically
promoting it to WT in i915_gem_object_pin_to_display_plane() when
the hardware is WT capable.

Supposedly the user wanted UC for a reason, so let's respect that.

Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
Just something that caught my eye while browsing the code. Can't really tell
how useful this would be.

 drivers/gpu/drm/i915/i915_gem.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 87d0aac..3251b53 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3823,6 +3823,7 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
 				     struct intel_ring_buffer *pipelined)
 {
 	u32 old_read_domains, old_write_domain;
+	unsigned int cache_level;
 	bool was_pin_display;
 	int ret;
 
@@ -3847,8 +3848,12 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
 	 * of uncaching, which would allow us to flush all the LLC-cached data
 	 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
 	 */
-	ret = i915_gem_object_set_cache_level(obj,
-					      HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
+	if (HAS_WT(obj->base.dev) && obj->cache_level != I915_CACHE_NONE)
+		cache_level = I915_CACHE_WT;
+	else
+		cache_level = I915_CACHE_NONE;
+
+	ret = i915_gem_object_set_cache_level(obj, cache_level);
 	if (ret)
 		goto err_unpin_display;
 
-- 
1.8.5.5