[Intel-gfx] [PATCH 6/7] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating

[Mika Kuoppala]

deepak.s at linux.intel.com writes:

> From: Deepak S <deepak.s at linux.intel.com>
>
> Signed-off-by: Deepak S <deepak.s at linux.intel.com>
> [vsyrjala: Fix merge fubmle where the code ended up in
> g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Acked-by: Ben Widawsky <ben at bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 08dcdc5..0b73a6d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4026,7 +4026,18 @@ static void cherryview_enable_rps(struct drm_device *dev)
>  		   GEN6_RP_UP_BUSY_AVG |
>  		   GEN6_RP_DOWN_IDLE_AVG);
>  
> +	/* ToDo: Update the mem freq based on latest spec [CHV]*/

Please do and consider fixing the vlv decoding. It seems to be off
too.

-Mika

>  	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> +	switch ((val >> 6) & 3) {
> +	case 0:
> +	case 1:
> +	case 2:
> +		dev_priv->mem_freq = 1600;
> +		break;
> +	case 3:
> +		dev_priv->mem_freq = 2000;
> +		break;
> +	}
>  
>  	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
>  	DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
> -- 
> 1.9.1
>
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