[Intel-gfx] [PATCH 67/71] drm/i915/chv: Try to program the PHY used clock channel overrides
Mika Kuoppala
mika.kuoppala at linux.intel.com
Tue May 27 15:08:06 CEST 2014
Mika Kuoppala <mika.kuoppala at linux.intel.com> writes:
> ville.syrjala at linux.intel.com writes:
>
>> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>>
>> These should make it possible to feed port C from pipe A or port B from
>> pipe B. Didn't quite seem to work though.
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 7 ++++++
>> drivers/gpu/drm/i915/intel_dp.c | 46 +++++++++++++++++++++++++++++++++++++++
>> drivers/gpu/drm/i915/intel_hdmi.c | 46 +++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 99 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 7056994..4bb733b 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -679,6 +679,8 @@ enum punit_power_well {
>>
>> #define _VLV_PCS_DW8_CH0 0x8220
>> #define _VLV_PCS_DW8_CH1 0x8420
>> +#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
>> +#define CHV_PCS_USEDCLKCHANNEL (1 << 21)
>> #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
>>
>> #define _VLV_PCS01_DW8_CH0 0x0220
>> @@ -803,6 +805,11 @@ enum punit_power_well {
>> #define DPIO_DCLKP_EN (1 << 13)
>> #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
>>
>> +#define _CHV_CMN_DW19_CH0 0x814c
>> +#define _CHV_CMN_DW6_CH1 0x8098
>> +#define CHV_CMN_USEDCLKCHANNEL (1 << 13)
>> +#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
>> +
>> #define CHV_CMN_DW30 0x8178
>> #define DPIO_LRC_BYPASS (1 << 3)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 9cbd702..9d6982e 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -2037,6 +2037,51 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
>> vlv_wait_port_ready(dev_priv, dport);
>> }
>>
>> +static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
>> +{
>> + struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
>> + struct drm_device *dev = encoder->base.dev;
>> + struct drm_i915_private *dev_priv = dev->dev_private;
>> + struct intel_crtc *intel_crtc =
>> + to_intel_crtc(encoder->base.crtc);
>> + enum dpio_channel ch = vlv_dport_to_channel(dport);
>> + enum pipe pipe = intel_crtc->pipe;
>> + u32 val;
>> +
>> + mutex_lock(&dev_priv->dpio_lock);
>> +
>> + /* program clock channel usage */
>> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
>> + val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
>> + if (pipe != PIPE_B)
>> + val &= ~CHV_PCS_USEDCLKCHANNEL;
>> + else
>> + val |= CHV_PCS_USEDCLKCHANNEL;
>> + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
>> +
>> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
>> + val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
>> + if (pipe != PIPE_B)
>> + val &= ~CHV_PCS_USEDCLKCHANNEL;
>> + else
>> + val |= CHV_PCS_USEDCLKCHANNEL;
>> + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
>> +
>> + /*
>> + * This a a bit weird since generally CL
>> + * matches the pipe, but here we need to
>> + * pick the CL based on the port.
>> + */
>> + val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
>
> Should we add setting bit 15 always in here?
Talked with Ville in rl. This is for fast pll lock and just
happens to be enabled in example modes.
> -Mika
>
>> + if (pipe != PIPE_B)
>> + val &= ~CHV_CMN_USEDCLKCHANNEL;
>> + else
>> + val |= CHV_CMN_USEDCLKCHANNEL;
>> + vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
>> +
>> + mutex_unlock(&dev_priv->dpio_lock);
>> +}
>> +
>> /*
>> * Native read with retry for link status and receiver capability reads for
>> * cases where the sink may still be asleep.
>> @@ -4134,6 +4179,7 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
>> intel_encoder->get_hw_state = intel_dp_get_hw_state;
>> intel_encoder->get_config = intel_dp_get_config;
>> if (IS_CHERRYVIEW(dev)) {
>> + intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
>> intel_encoder->pre_enable = chv_pre_enable_dp;
>> intel_encoder->enable = vlv_enable_dp;
>> intel_encoder->post_disable = chv_post_disable_dp;
>> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
>> index d2b1186..d36f74c 100644
>> --- a/drivers/gpu/drm/i915/intel_hdmi.c
>> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
>> @@ -1186,6 +1186,51 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
>> mutex_unlock(&dev_priv->dpio_lock);
>> }
>>
>> +static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
>> +{
>> + struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
>> + struct drm_device *dev = encoder->base.dev;
>> + struct drm_i915_private *dev_priv = dev->dev_private;
>> + struct intel_crtc *intel_crtc =
>> + to_intel_crtc(encoder->base.crtc);
>> + enum dpio_channel ch = vlv_dport_to_channel(dport);
>> + enum pipe pipe = intel_crtc->pipe;
>> + u32 val;
>> +
>> + mutex_lock(&dev_priv->dpio_lock);
>> +
>> + /* program clock channel usage */
>> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
>> + val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
>> + if (pipe != PIPE_B)
>> + val &= ~CHV_PCS_USEDCLKCHANNEL;
>> + else
>> + val |= CHV_PCS_USEDCLKCHANNEL;
>> + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
>> +
>> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
>> + val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
>> + if (pipe != PIPE_B)
>> + val &= ~CHV_PCS_USEDCLKCHANNEL;
>> + else
>> + val |= CHV_PCS_USEDCLKCHANNEL;
>> + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
>> +
>> + /*
>> + * This a a bit weird since generally CL
>> + * matches the pipe, but here we need to
>> + * pick the CL based on the port.
>> + */
>> + val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
>> + if (pipe != PIPE_B)
>> + val &= ~CHV_CMN_USEDCLKCHANNEL;
>> + else
>> + val |= CHV_CMN_USEDCLKCHANNEL;
>> + vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
>> +
>> + mutex_unlock(&dev_priv->dpio_lock);
>> +}
>> +
>> static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
>> {
>> struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
>> @@ -1486,6 +1531,7 @@ void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
>> intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
>> intel_encoder->get_config = intel_hdmi_get_config;
>> if (IS_CHERRYVIEW(dev)) {
>> + intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
>> intel_encoder->pre_enable = chv_hdmi_pre_enable;
>> intel_encoder->enable = vlv_enable_hdmi;
>> intel_encoder->post_disable = chv_hdmi_post_disable;
>> --
>> 1.8.3.2
>>
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