[Intel-gfx] [PATCH v2 69/71] drm/i915/chv: Force PHY clock buffers off after PLL disable

[Mika Kuoppala]

ville.syrjala at linux.intel.com writes:

> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> Now that we forced the clock buffers on in .pre_pll_enable() we
> should probably undo the damage after we've turned the PLL off.
>
> We do the clock buffer force enable in the .pre_pll_enable() hook
> as we need to know which port is going to be used, but in the disable
> case we don't need the port since we just disable the clock buffers
> to both channels. So we can do this in chv_disable_pll() instead
> of having to add any kind of .post_pll_disable() hook.
>
> v2: Improve the commit message
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Reviewed-by: Mika Kuoppala <mika.kuoppala at intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3215169..376f6c3 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1699,6 +1699,17 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
>  	val &= ~DPIO_DCLKP_EN;
>  	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
>  
> +	/* disable left/right clock distribution */
> +	if (pipe != PIPE_B) {
> +		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
> +		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
> +		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
> +	} else {
> +		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
> +		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
> +		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
> +	}
> +
>  	mutex_unlock(&dev_priv->dpio_lock);
>  }
>  
> -- 
> 1.8.5.5
>
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