[Intel-gfx] [PATCH v2 6/6] drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv

[Damien Lespiau]

On Mon, Mar 24, 2014 at 11:00:07PM +0530, sourab.gupta at intel.com wrote:
> From: Akash Goel <akash.goel at intel.com>
> 
> For disabling L3 clock gating we need to set bit 25 of MMIO
> register 940c. Earlier this was being done by just writing 1
> into bit 25 and resetting all other bits.
> This patch modifies the routine to read-modify-write of the
> register, so that the values of other bits are not destroyed.
> 
> v2: Modifying the comments and the patch commit message (Chris)
> 
> Signed-off-by: Akash Goel <akash.goel at intel.com>
> Signed-off-by: Sourab Gupta <sourab.gupta at intel.com>

Apart from the multiline comment format and the second line not aligned
with the '(' as we usually do:

Reviewed-by: Damien Lespiau <damien.lespiau at intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c3a8554..af4bb8e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5093,8 +5093,11 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(GEN6_UCGCTL2,
>  		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
>  
> -	/* WaDisableL3Bank2xClockGate:vlv */
> -	I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
> +	/* WaDisableL3Bank2xClockGate:vlv
> +	 * Disabling L3 clock gating- MMIO 940c[25] = 1
> +	 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
> +	I915_WRITE(GEN7_UCGCTL4,
> +			I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
>  
>  	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
>  
> -- 
> 1.8.5.1
>