[Intel-gfx] [PATCH 0/4] drm/i915: Gen2/3 C3 wakeup stuff

[Chris Wilson]

On Tue, Feb 25, 2014 at 03:13:37PM +0200, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> I tried to fix the C3 vs. vblank interrupt issues reportd in [1], but
> it looks like the AGPBUSY# stuff doesn't help there for some reason. I
> guess either the board isn't wired correctly, or we're missing
> something else. I doubt the BM wakup mechanism itself would be
> broken since then I would expect the machine to lock up when someone
> does DMA while in C3. IIRC I actually had that kind of an issue on
> some old VIA chipset long ago.
> 
> Anyways, my 855gm actually supports C3, and on that machine the MI_STATE
> AGPBUSY# stuff is effective. So I'm going to assume that gen3 behaviour
> should match, and so I'm just sticking it all into .init_clock_gating()
> for both gen2 and gen3.
> 
> I also found another gen3 C3 bit in i915_gem_load(). I think it would
> be better to collect that into .init_clock_gating() as well. But I left
> it also in i915_gem_load() for UMS.
> 
> [1] https://bugs.freedesktop.org/show_bug.cgi?id=30364
> 
> Ville Syrjälä (4):
>   drm/i915: Set AGPBUSY# bit in init_clock_gating
>   drm/i915: Flip the sense of AGPBUSY_DIS bit
>   drm/i915: Enable interrupt-based AGPBUSY# enable on 85x
>   drm/i915: Move the C3 LP write bit setup to gen3_init_clock_gating()
>     for KMS

They all look sensible, seem to better match the docs than the
existing code and make the code easier to read (apart from the
UMS frobbing!), so:

Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>

The slow vblank delivery issue remains iirc though.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre