[Intel-gfx] [PATCH] drm/i915: vlv: fix stuck primary plane due to SR watermarks

[Imre Deak]

Blanking/unblanking the console in a loop on an Asus T100 sometimes
leaves the console blank. After some digging I found that applying

commit 61bc95c1fbbb6a08b55bbe161fdf1ea5493fc595
Author: Egbert Eich <eich at suse.com>
Date:   Mon Mar 4 09:24:38 2013 -0500

    DRM/i915: On G45 enable cursor plane briefly after enabling the display plane.

fixed VLV too. At least in my case the problem seems to happen already
during the previous crtc disabling, and it goes away if we disable SR
watermarks before disabling the primary plane.

I also noticed that the problem only happens if the C7S CPU idle state
is entered, disabling that also gets rid of the problem. As an
alternative I also tried to increase the plane SR watermark close to its
maximum but that didn't solve the issue.

Signed-off-by: Imre Deak <imre.deak at intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      | 1 +
 drivers/gpu/drm/i915/intel_display.c | 9 +++++++++
 drivers/gpu/drm/i915/intel_pm.c      | 7 +++++++
 3 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bea9ab40..afee677 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2591,6 +2591,7 @@ extern void gen6_set_rps(struct drm_device *dev, u8 val);
 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
+extern void valleyview_disable_sr_watermarks(struct drm_i915_private *dev_priv);
 extern void intel_detect_pch(struct drm_device *dev);
 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
 extern int intel_enable_rc6(const struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 54095d4..11611e1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4767,6 +4767,15 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
 	if (IS_GEN2(dev))
 		intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
 
+	/*
+	 * Having the SR WMs enabled when disabling the primary plane may
+	 * leave the primary plane in a stuck state, where it wouldn't
+	 * start fetching pixels after a subsequent crtc enable.
+	 * The WMs will be set to their proper values again when calling
+	 * intel_update_watermarks() next.
+	 */
+	if (IS_VALLEYVIEW(dev))
+		valleyview_disable_sr_watermarks(dev_priv);
 	intel_crtc_disable_planes(crtc);
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1840d15..01962aa 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1306,6 +1306,13 @@ static void vlv_update_drain_latency(struct drm_device *dev)
 	}
 }
 
+void valleyview_disable_sr_watermarks(struct drm_i915_private *dev_priv)
+{
+	I915_WRITE(FW_BLC_SELF_VLV,
+		   I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
+	POSTING_READ(FW_BLC_SELF_VLV);
+}
+
 #define single_plane_enabled(mask) is_power_of_2(mask)
 
 static void valleyview_update_wm(struct drm_crtc *crtc)
-- 
1.8.4