[Intel-gfx] [PATCH 2/2] drm/i915: Check pipe_config.has_dp_encoder instead of encoder types
Ander Conselvan de Oliveira
conselvan2 at gmail.com
Tue Nov 4 10:35:14 CET 2014
On 11/03/2014 03:40 PM, Daniel Vetter wrote:
> More concise. Noticed while reviewing Ander's patch which touched a
> lot of the pipe_has_type checks.
>
> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 9 +++------
> 1 file changed, 3 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 5eb12ed11df5..f7e751bcccb1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3784,9 +3784,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
> intel_fdi_normal_train(crtc);
>
> /* For PCH DP, enable TRANS_DP_CTL */
> - if (HAS_PCH_CPT(dev) &&
> - (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT) ||
> - intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_EDP))) {
> + if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) {
> u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
> reg = TRANS_DP_CTL(pipe);
> temp = I915_READ(reg);
> @@ -5865,8 +5863,7 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
> vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
> 0x00d0000f);
>
> - if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP) ||
> - intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
> + if (crtc->config.has_dp_encoder) {
> /* Use SSC source */
> if (pipe == PIPE_A)
> vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
> @@ -6056,7 +6053,7 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
> if (is_sdvo)
> dpll |= DPLL_SDVO_HIGH_SPEED;
>
> - if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
> + if (crtc->config.has_dp_encoder)
crtc->new_config ?
> dpll |= DPLL_SDVO_HIGH_SPEED;
>
> /* compute bitmask from p1 value */
>
More information about the Intel-gfx
mailing list