[Intel-gfx] [PATCH 00/28] SKL stage 1, a few more patches

[Damien Lespiau]

We might as well try to push a few more patches while waiting for the next
batch of reviews. Here's the WM code and 2 bonus patches around forcewake and
rc6.

The attentive reader will notice the lack of r-b tag for:
  "drm/i915/skl: Make res_blocks/lines intermediate values 32 bits"

This patch does address the known review comment though. At some point we have
to be realistic about our process, try to push stuff forward anyway, and have
confidence we can fix problems when they arise, especially when the risk is low
(new platform code, not running on any of the previous platforms).

Next stop. SKL clocks.

-- 
Damien

Damien Lespiau (19):
  drm/i915/skl: Add DDB allocation management structures
  drm/i915/skl: Allocate DDB portions for display planes
  drm/i915/skl: Program the DDB allocation
  drm/i915/skl: Store the new WM state at the very end of the update
  drm/i915/skl: Read back the DDB allocation hw state
  drm/i915/skl: Augment the latency debugfs files for SKL
  drm/i915/skl: Add a debugfs file to dump the DDB allocation
  drm/i915/skl: Check the DDB state at modeset
  drm/i915/skl: Make 'end' of the DDB allocation entry exclusive
  drm/i915/skl: Use a more descriptive parameter name in
    skl_compute_plane_wm()
  drm/i915/skl: Make res_blocks/lines intermediate values 32 bits
  drm/i915/skl: Reduce the number of holes in struct skl_wm_level
  drm/i915/skl: Move all the WM compute functions in one place
  drm/i915/skl: Rework when the transition WMs are computed
  drm/i915/skl: Correctly align skl_compute_plane_wm() arguments
  drm/i915/skl: Reduce the indentation level in skl_write_wm_values()
  drm/i915/skl: Stage the pipe DDB allocation
  drm/i915/skl: Flush the WM configuration
  drm/i915/skl: Log the order in which we flush the pipes in the WM code

Pradeep Bhat (5):
  drm/i915/skl: Read the Memory Latency Values for WM computation
  drm/i915/skl: Register definitions and macros for SKL Watermark regs
  drm/i915/skl: Definition of SKL WM param structs for pipe/plane
  drm/i915/skl: SKL Watermark Computation
  drm/i915/skl: Read the pipe WM HW state

Vandana Kannan (2):
  drm/i915/gen9: Add 2us read latency to WM level
  drm/i915/gen9: Disable WM if corresponding latency is 0

Zhe Wang (2):
  drm/i915/skl: Gen9 Forcewake
  drm/i915/skl: Enable Gen9 RC6

 drivers/gpu/drm/i915/i915_debugfs.c  |  113 +++-
 drivers/gpu/drm/i915/i915_drv.h      |   66 ++-
 drivers/gpu/drm/i915/i915_reg.h      |   64 +++
 drivers/gpu/drm/i915/intel_display.c |   55 +-
 drivers/gpu/drm/i915/intel_drv.h     |   11 +
 drivers/gpu/drm/i915/intel_pm.c      | 1034 +++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_uncore.c  |  175 +++++-
 7 files changed, 1493 insertions(+), 25 deletions(-)

-- 
1.8.3.1