[Intel-gfx] [PATCH] drm/i915: Disable caches for Global GTT.

[Daniel Vetter]

On Thu, Oct 30, 2014 at 5:18 PM, Rodrigo Vivi <rodrigo.vivi at intel.com> wrote:
> Global GTT doesn't have pat_sel[2:0] so it always point to pat_sel = 000;
> So the only way to avoid screen corruptions is setting PAT 0 to Uncached.
>
> MOCS can still be used though. But if userspace is trusting PTE for
> cache selection the safest thing to do is to let caches disabled.
>
> BSpec: "For GGTT, there is NO pat_sel[2:0] from the entry,
> so RTL will always use the value corresponding to pat_sel = 000"
>
> Reference: https://bugs.freedesktop.org/show_bug.cgi?id=85576
> Cc: James Ausmus <james.ausmus at intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>

Ok, I think this is -fixes + cc: stable material, but we need to be a
bit more elaborate on the commit message:

- System agent ggtt writes (i.e. cpu gtt mmaps) already work before
this patch, i.e. the same uncached + snooping access like on gen6/7
seems to be in effect.
- So this just fixes blitter/render access. Again it looks like it's
not just uncached access, but uncached + snooping. So we can still
hold onto all our assumptions wrt cpu clflushing on LLC machines.

I think this should be both in the commit message and code.

Chris, please correct if I've summarized this wrongly.

Thanks, Daniel

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch