[Intel-gfx] [PATCH] drm/i915: WaSetupGtModeTdRowDispatch:snb

[Ville Syrjälä]

On Fri, Nov 14, 2014 at 09:25:29AM +0100, Daniel Vetter wrote:
> This reverts
> 
> commit 8d85d27281095e4df6eb97ae84326b5814337337
> Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Date:   Tue Feb 4 21:59:15 2014 +0200
> 
>     drm/i915: Fix SNB GT_MODE register setup

I think you mean

commit 6547fbdbfff62c99e4f7b4f985ff8b3454f33b0f
Author: Daniel Vetter <daniel.vetter at ffwll.ch>
Date:   Fri Dec 14 23:38:29 2012 +0100

    drm/i915: Implement WaSetupGtModeTdRowDispatch

> 
> Reported-by: Leo Wolf <jclw at ymail.com>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79996
> Cc: stable at vger.kernel.org
> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 5 -----
>  1 file changed, 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9e87265f2448..03417a38cd09 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6472,11 +6472,6 @@ static void gen6_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(_3D_CHICKEN,
>  		   _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
>  
> -	/* WaSetupGtModeTdRowDispatch:snb */
> -	if (IS_SNB_GT1(dev))
> -		I915_WRITE(GEN6_GT_MODE,
> -			   _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
> -
>  	/* WaDisable_RenderCache_OperationalFlush:snb */
>  	I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
>  
> -- 
> 2.1.1
> 
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-- 
Ville Syrjälä
Intel OTC