[Intel-gfx] [PATCH 06/18] drm/i915: Assume 400 MHz cdclk for the rest of gen4-7

[Daniel Vetter]

On Mon, Nov 17, 2014 at 04:43:40PM +0200, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> We don't currently have cdclk extraction code for 965g,snb,ivb.
> Let's assumee 400 MHz until we know better. That seems to match hints
> in various vague documents. Whether that's good enough is not
> entirely clear.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Hm, not sure whether these chips even had outputs which could drive this
high really. And if we now start rejecting modes that previously worked
(really unlikely imo) we'll get the regression reports and can fudge the
numbers some more. So even without more spec hints I'm totally fine with
going forward with this.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch