[Intel-gfx] [PATCH 11/18] drm/i915: Use cached cdclk value

[Ville Syrjälä]

On Mon, Nov 17, 2014 at 07:41:44PM +0100, Daniel Vetter wrote:
> On Mon, Nov 17, 2014 at 04:43:45PM +0200, ville.syrjala at linux.intel.com wrote:
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index d8841c7..d23aa05 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -1401,6 +1401,6 @@ int i915_get_cdclk_freq(void)
> >  	dev_priv = container_of(hsw_pwr, struct drm_i915_private,
> >  				power_domains);
> >  
> > -	return dev_priv->display.get_display_clock_speed(dev_priv->dev);
> > +	return dev_priv->cdclk_freq;
> 
> Maybe this here is the reason why hsw shouldn't change cdclck - the audio
> side just falls over?

I must admit that I didn't check whether the audio side will query the
cdclk again after every mode change. It really should, but often reality
doesn't match my expectations :)

-- 
Ville Syrjälä
Intel OTC