[Intel-gfx] [PATCH] drm/i915: Read power well status before other registers for drpc info

Deepak S deepak.s at linux.intel.com
Fri Nov 21 04:26:02 CET 2014


On Wednesday 19 November 2014 11:37 PM, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> Trying to read the status of the power wells right after taking forcewake
> for the other register reads makes little sense. Most of the time the
> power wells will still be up due to the recent forcewake. Instead do the
> power well status read first, and only then read the register needing
> forcewake. This way the reported power well status can actually reflect
> what's going on in the system.
>
> Cc: Deepak S <deepak.s at intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_debugfs.c | 9 ++++-----
>   1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 319da61..2d4f870 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1240,11 +1240,12 @@ static int vlv_drpc_info(struct seq_file *m)
>   	struct drm_info_node *node = m->private;
>   	struct drm_device *dev = node->minor->dev;
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> -	u32 rpmodectl1, rcctl1;
> +	u32 rpmodectl1, rcctl1, pw_status;
>   	unsigned fw_rendercount = 0, fw_mediacount = 0;
>   
>   	intel_runtime_pm_get(dev_priv);
>   
> +	pw_status = I915_READ(VLV_GTLC_PW_STATUS);
>   	rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
>   	rcctl1 = I915_READ(GEN6_RC_CONTROL);
>   
> @@ -1263,11 +1264,9 @@ static int vlv_drpc_info(struct seq_file *m)
>   		   yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
>   					GEN6_RC_CTL_EI_MODE(1))));
>   	seq_printf(m, "Render Power Well: %s\n",
> -			(I915_READ(VLV_GTLC_PW_STATUS) &
> -				VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
> +		   (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
>   	seq_printf(m, "Media Power Well: %s\n",
> -			(I915_READ(VLV_GTLC_PW_STATUS) &
> -				VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
> +		   (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
>   
>   	seq_printf(m, "Render RC6 residency since boot: %u\n",
>   		   I915_READ(VLV_GT_RENDER_RC6));

Reviewed-by: Deepak S<deepak.s at linux.intel.com>




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