[Intel-gfx] [PATCH 1/5] drm/i915: Try to avoid pps_{lock, unlock}() on DP ports

Egbert Eich eich at suse.de
Mon Nov 24 18:16:23 CET 2014


From: Ville Syrjälä <ville.syrjala at linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 48 ++++++++++++++++++++++++-----------------
 1 file changed, 28 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 81f959d..a24c8cc7 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -807,17 +807,19 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 	uint32_t status;
 	int try, clock = 0;
 	bool has_aux_irq = HAS_AUX_IRQ(dev);
-	bool vdd;
+	bool vdd = false;
 
-	pps_lock(intel_dp);
+	if (is_edp(intel_dp)) {
+		pps_lock(intel_dp);
 
-	/*
-	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
-	 * In such cases we want to leave VDD enabled and it's up to upper layers
-	 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
-	 * ourselves.
-	 */
-	vdd = edp_panel_vdd_on(intel_dp);
+		/*
+		 * We will be called with VDD already enabled for dpcd/edid/oui reads.
+		 * In such cases we want to leave VDD enabled and it's up to upper layers
+		 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
+		 * ourselves.
+		 */
+		vdd = edp_panel_vdd_on(intel_dp);
+	}
 
 	/* dp aux is extremely sensitive to irq latency, hence request the
 	 * lowest possible wakeup latency and so prevent the cpu from going into
@@ -924,10 +926,12 @@ out:
 	pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 	intel_aux_display_runtime_put(dev_priv);
 
-	if (vdd)
-		edp_panel_vdd_off(intel_dp, false);
+	if (is_edp(intel_dp)) {
+		if (vdd)
+			edp_panel_vdd_off(intel_dp, false);
 
-	pps_unlock(intel_dp);
+		pps_unlock(intel_dp);
+	}
 
 	return ret;
 }
@@ -2291,18 +2295,22 @@ static void intel_enable_dp(struct intel_encoder *encoder)
 	if (WARN_ON(dp_reg & DP_PORT_EN))
 		return;
 
-	pps_lock(intel_dp);
+	if (is_edp(intel_dp)) {
+		pps_lock(intel_dp);
 
-	if (IS_VALLEYVIEW(dev))
-		vlv_init_panel_power_sequencer(intel_dp);
+		if (IS_VALLEYVIEW(dev))
+			vlv_init_panel_power_sequencer(intel_dp);
 
-	intel_dp_enable_port(intel_dp);
+		intel_dp_enable_port(intel_dp);
 
-	edp_panel_vdd_on(intel_dp);
-	edp_panel_on(intel_dp);
-	edp_panel_vdd_off(intel_dp, true);
+		edp_panel_vdd_on(intel_dp);
+		edp_panel_on(intel_dp);
+		edp_panel_vdd_off(intel_dp, true);
 
-	pps_unlock(intel_dp);
+		pps_unlock(intel_dp);
+	} else {
+		intel_dp_enable_port(intel_dp);
+	}
 
 	if (IS_VALLEYVIEW(dev))
 		vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));
-- 
1.8.4.5




More information about the Intel-gfx mailing list