[Intel-gfx] [PATCH 3/4] drm/i915: Make sure hardware uses the correct swing margin/deemph bits on chv

[Mika Kuoppala]

ville.syrjala at linux.intel.com writes:

> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> The register can house two different swing marging/deemph settings at
> once. However only one gets used based on some other bits. Make sure we
> set those bits correctly to make the hardware use the settings we
> provided.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Reviewed-by: Mika Kuoppala <mika.kuoppala at intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h   | 19 +++++++++++++++++++
>  drivers/gpu/drm/i915/intel_dp.c   | 14 ++++++++++++++
>  drivers/gpu/drm/i915/intel_hdmi.c | 14 ++++++++++++++
>  3 files changed, 47 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2df946d..b8e8d33 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -824,12 +824,31 @@ enum punit_power_well {
>  
>  #define _VLV_PCS_DW9_CH0		0x8224
>  #define _VLV_PCS_DW9_CH1		0x8424
> +#define   DPIO_PCS_TX2MARGIN_MASK	(0x7<<13)
> +#define   DPIO_PCS_TX2MARGIN_000	(0<<13)
> +#define   DPIO_PCS_TX2MARGIN_101	(1<<13)
> +#define   DPIO_PCS_TX1MARGIN_MASK	(0x7<<10)
> +#define   DPIO_PCS_TX1MARGIN_000	(0<<10)
> +#define   DPIO_PCS_TX1MARGIN_101	(1<<10)
>  #define	VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
>  
> +#define _VLV_PCS01_DW9_CH0		0x224
> +#define _VLV_PCS23_DW9_CH0		0x424
> +#define _VLV_PCS01_DW9_CH1		0x2624
> +#define _VLV_PCS23_DW9_CH1		0x2824
> +#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
> +#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
> +
>  #define _CHV_PCS_DW10_CH0		0x8228
>  #define _CHV_PCS_DW10_CH1		0x8428
>  #define   DPIO_PCS_SWING_CALC_TX0_TX2	(1<<30)
>  #define   DPIO_PCS_SWING_CALC_TX1_TX3	(1<<31)
> +#define   DPIO_PCS_TX2DEEMP_MASK	(0xf<<24)
> +#define   DPIO_PCS_TX2DEEMP_9P5		(0<<24)
> +#define   DPIO_PCS_TX2DEEMP_6P0		(2<<24)
> +#define   DPIO_PCS_TX1DEEMP_MASK	(0xf<<16)
> +#define   DPIO_PCS_TX1DEEMP_9P5		(0<<16)
> +#define   DPIO_PCS_TX1DEEMP_6P0		(2<<16)
>  #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
>  
>  #define _VLV_PCS01_DW10_CH0		0x0228
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index e5ada4f..f8e4578 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2632,12 +2632,26 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
>  	/* Clear calc init */
>  	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
>  	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> +	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
> +	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
>  	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
>  
>  	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
>  	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> +	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
> +	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
>  	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
>  
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
> +	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
> +	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
> +	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
> +	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
> +
>  	/* Program swing deemph */
>  	for (i = 0; i < 4; i++) {
>  		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 9169786..f3bf0c7 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1414,12 +1414,26 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
>  	/* Clear calc init */
>  	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
>  	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> +	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
> +	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
>  	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
>  
>  	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
>  	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> +	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
> +	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
>  	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
>  
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
> +	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
> +	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
> +	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
> +	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
> +
>  	/* FIXME: Program the support xxx V-dB */
>  	/* Use 800mV-0dB */
>  	for (i = 0; i < 4; i++) {
> -- 
> 1.8.5.5
>
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