[Intel-gfx] [PATCH v2 4/4] drm/i915: Clear TX FIFO reset master override bits on chv

[Daniel Vetter]

On Thu, Oct 02, 2014 at 05:33:05PM +0300, Mika Kuoppala wrote:
> ville.syrjala at linux.intel.com writes:
> 
> > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> >
> > Clear the override bits to make sure the hardware maanages
> > the TX FIFO reset master on its own.
> >
> > v2: Squash with the earlier attempt at forcing the override bits
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Reviewed-by: Mika Kuoppala <mika.kuoppala at intel.com>

Remaining two patches from this series merged, thanks.
-Daniel

> 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h   | 12 ++++++++++++
> >  drivers/gpu/drm/i915/intel_dp.c   |  9 +++++++++
> >  drivers/gpu/drm/i915/intel_hdmi.c |  9 +++++++++
> >  3 files changed, 30 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index b8e8d33..daac02b 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -784,6 +784,8 @@ enum punit_power_well {
> >  #define _VLV_PCS_DW0_CH1		0x8400
> >  #define   DPIO_PCS_TX_LANE2_RESET	(1<<16)
> >  #define   DPIO_PCS_TX_LANE1_RESET	(1<<7)
> > +#define   DPIO_LEFT_TXFIFO_RST_MASTER2	(1<<4)
> > +#define   DPIO_RIGHT_TXFIFO_RST_MASTER2	(1<<3)
> >  #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
> >  
> >  #define _VLV_PCS01_DW0_CH0		0x200
> > @@ -860,8 +862,18 @@ enum punit_power_well {
> >  
> >  #define _VLV_PCS_DW11_CH0		0x822c
> >  #define _VLV_PCS_DW11_CH1		0x842c
> > +#define   DPIO_LANEDESKEW_STRAP_OVRD	(1<<3)
> > +#define   DPIO_LEFT_TXFIFO_RST_MASTER	(1<<1)
> > +#define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1<<0)
> >  #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
> >  
> > +#define _VLV_PCS01_DW11_CH0		0x022c
> > +#define _VLV_PCS23_DW11_CH0		0x042c
> > +#define _VLV_PCS01_DW11_CH1		0x262c
> > +#define _VLV_PCS23_DW11_CH1		0x282c
> > +#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
> > +#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
> > +
> >  #define _VLV_PCS_DW12_CH0		0x8230
> >  #define _VLV_PCS_DW12_CH1		0x8430
> >  #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index f8e4578..4f69648 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -2223,6 +2223,15 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
> >  
> >  	mutex_lock(&dev_priv->dpio_lock);
> >  
> > +	/* allow hardware to manage TX FIFO reset source */
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> > +	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> > +
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> > +	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> > +
> >  	/* Deassert soft data lane reset*/
> >  	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
> >  	val |= CHV_PCS_REQ_SOFTRESET_EN;
> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> > index f3bf0c7..f0cff45 100644
> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > @@ -1378,6 +1378,15 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
> >  
> >  	mutex_lock(&dev_priv->dpio_lock);
> >  
> > +	/* allow hardware to manage TX FIFO reset source */
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> > +	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> > +
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> > +	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> > +
> >  	/* Deassert soft data lane reset*/
> >  	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
> >  	val |= CHV_PCS_REQ_SOFTRESET_EN;
> > -- 
> > 1.8.5.5
> >
> > _______________________________________________
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch