[Intel-gfx] [PATCH 0/3] Rework of the WM flush (for the DDB allocation)

[Damien Lespiau]

Ville found that the sequencing I had to re-program the DDB wasn't quite
correct and so this is an attempt to do better.

This series reworks patch:

  [PATCH 78/89] drm/i915/skl: Flush the WM configuration

of the initial SKL Stage 1 series. The core of the issue is now documented in a
comment, so I won't repeat it here again.

-- 
Damien

Damien Lespiau (3):
  drm/i915/skl: Stage the pipe DDB allocation
  drm/i915/skl: Flush the WM configuration
  drm/i915/skl: Log the order in which we flush the pipes in the WM code

 drivers/gpu/drm/i915/i915_drv.h |   1 +
 drivers/gpu/drm/i915/intel_pm.c | 152 ++++++++++++++++++++++++++++++++++++++--
 2 files changed, 146 insertions(+), 7 deletions(-)

-- 
1.8.3.1