[Intel-gfx] [PATCH 3/3] drm/i915/skl: Log the order in which we flush the pipes in the WM code

[Damien Lespiau]

Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 99f7c40..178b35f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3531,11 +3531,14 @@ static void skl_write_wm_values(struct drm_i915_private *dev_priv,
  * We need to sequence the re-allocation: C, B, A (and not B, C, A).
  */
 
-static void skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
+static void
+skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
 {
 	struct drm_device *dev = dev_priv->dev;
 	int plane;
 
+	DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
+
 	for_each_plane(pipe, plane) {
 		I915_WRITE(PLANE_SURF(pipe, plane),
 			   I915_READ(PLANE_SURF(pipe, plane)));
@@ -3586,7 +3589,7 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
 		if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
 			continue;
 
-		skl_wm_flush_pipe(dev_priv, pipe);
+		skl_wm_flush_pipe(dev_priv, pipe, 1);
 		intel_wait_for_vblank(dev, pipe);
 
 		reallocated[pipe] = true;
@@ -3611,7 +3614,7 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
 
 		if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
 		    skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
-			skl_wm_flush_pipe(dev_priv, pipe);
+			skl_wm_flush_pipe(dev_priv, pipe, 2);
 			intel_wait_for_vblank(dev, pipe);
 		}
 
@@ -3637,7 +3640,7 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
 		if (reallocated[pipe])
 			continue;
 
-		skl_wm_flush_pipe(dev_priv, pipe);
+		skl_wm_flush_pipe(dev_priv, pipe, 3);
 	}
 }
 
-- 
1.8.3.1