[Intel-gfx] [PATCH 0/8] Stage shared dpll config

[Ander Conselvan de Oliveira]

This series changes the mode set sequence so that the clock and PLL
logic that was done in the *_crtc_mode_set() hooks is done before
disabling crtcs. This avoids having to restore the old configuration
in the case of failure, since the hardware was never touched.

Ander Conselvan de Oliveira (8):
  drm/i915: Convert shared dpll reference count to a crtc mask
  drm/i915: Move dpll crtc_mask and hw_state fields into separate struct
  drm/i915: Add infrastructure for choosing DPLLs before disabling crtcs
  drm/i915: Covert HSW+ to choose DPLLS before disabling CRTCs
  drm/i915: Covert ILK-IVB to choose DPLLS before disabling CRTCs
  drm/i915: Covert remaining platforms to choose DPLLS before disabling
    CRTCs
  drm/i915: Remove crtc_mode_set() hook
  drm/i915: Don't store current shared DPLL in the new pipe_config

 drivers/gpu/drm/i915/i915_debugfs.c  |  15 +--
 drivers/gpu/drm/i915/i915_drv.h      |  16 +--
 drivers/gpu/drm/i915/intel_ddi.c     |   6 +-
 drivers/gpu/drm/i915/intel_display.c | 197 +++++++++++++++++++++++------------
 4 files changed, 150 insertions(+), 84 deletions(-)

-- 
1.9.1