[Intel-gfx] [PATCH V2] drm/i915: Change order of operations for VLV/CHV to not train DP link before PHYs are ready

[Todd Previte]

On 10/21/2014 7:41 AM, Daniel Vetter wrote:
> On Fri, Oct 17, 2014 at 11:41:12AM -0700, Todd Previte wrote:
>> V2 changes:-+
>> - Moved the intel_dp_enable_port() call out of intel_dp_enable() and placed it
>>    before the calls to intel_dp_enable() and vlv_wait_port_ready()
>> - Cleaned up a spacing issues with the code indents
>> - Amended the commit message to be under 80 characters per line and expanded
>>    on the description of what the patch does
> The per-patch commit log should be part of the commit message, above the
> sob section. Some kernel maintainers want it below claiming it's noise,
> but I disagree. In any case it needs to be part of the patch when
> submitting it.
>
> The cover letter changelog is just for the big stuff spawning more than
> one patch when you have a big series.
> -Daniel

Ville's patch (patch 07/17) in the CHV PPS fix sequence is going to pick 
up most of the necessary changes that are included here. The one aspect 
that is not covered is that link training needs to be skipped when the 
PHYs are down. If that change is integrated into his patch, this patch 
is not necessary. Otherwise, this patch will need to be updated to 
accommodate that change.

-T