[Intel-gfx] [PATCH] drm/i915: Emit even number of dwords when emitting LRIs

[Daniel Vetter]

On Wed, Oct 22, 2014 at 06:59:52PM +0100, Arun Siluvery wrote:
> The number of DWords should be even when doing ring emits as
> command sequences require QWord alignment.
> 
> v2: user LRI variant that can write multiple regs in one go (Damien).
> We can simply insert one NOP at the end instead of one per register write.
> 
> Cc: Mika Kuoppala <mika.kuoppala at intel.com>
> Signed-off-by: Arun Siluvery <arun.siluvery at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 497b836..a8f72e8 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -680,15 +680,16 @@ static int intel_ring_workarounds_emit(struct intel_engine_cs *ring)
>  	if (ret)
>  		return ret;
>  
> -	ret = intel_ring_begin(ring, w->count * 3);
> +	ret = intel_ring_begin(ring, (w->count * 2 + 2));
>  	if (ret)
>  		return ret;
>  
> +	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));

Afaik there's a limit to the size of an MI_LRI. Where's the check for
that (probably with a WARN_ON for now to avoid unecessary complexity)?
-Daniel

>  	for (i = 0; i < w->count; i++) {
> -		intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
>  		intel_ring_emit(ring, w->reg[i].addr);
>  		intel_ring_emit(ring, w->reg[i].value);
>  	}
> +	intel_ring_emit(ring, MI_NOOP);
>  
>  	intel_ring_advance(ring);
>  
> -- 
> 2.1.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch