[Intel-gfx] [PATCH] drm/i915: Emit even number of dwords when emitting LRIs

[Ville Syrjälä]

On Thu, Oct 23, 2014 at 01:50:23PM +0100, Chris Wilson wrote:
> On Thu, Oct 23, 2014 at 01:42:38PM +0100, Damien Lespiau wrote:
> > On Thu, Oct 23, 2014 at 02:21:02PM +0200, Daniel Vetter wrote:
> > > On Wed, Oct 22, 2014 at 06:59:52PM +0100, Arun Siluvery wrote:
> > > > The number of DWords should be even when doing ring emits as
> > > > command sequences require QWord alignment.
> > > > 
> > > > v2: user LRI variant that can write multiple regs in one go (Damien).
> > > > We can simply insert one NOP at the end instead of one per register write.
> > > > 
> > > > Cc: Mika Kuoppala <mika.kuoppala at intel.com>
> > > > Signed-off-by: Arun Siluvery <arun.siluvery at linux.intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++--
> > > >  1 file changed, 3 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > > > index 497b836..a8f72e8 100644
> > > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > > > @@ -680,15 +680,16 @@ static int intel_ring_workarounds_emit(struct intel_engine_cs *ring)
> > > >  	if (ret)
> > > >  		return ret;
> > > >  
> > > > -	ret = intel_ring_begin(ring, w->count * 3);
> > > > +	ret = intel_ring_begin(ring, (w->count * 2 + 2));
> > > >  	if (ret)
> > > >  		return ret;
> > > >  
> > > > +	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
> > > 
> > > Afaik there's a limit to the size of an MI_LRI. Where's the check for
> > > that (probably with a WARN_ON for now to avoid unecessary complexity)?
> > 
> > I guess there's always the size of the length field, I don't see any
> > other indication. Note that I can find the documentation of the
> > multi-registers version of LRI either. So, well, we probably should
> > double check it does work.
> 
> It does work. The max is around 60 iirc (the max length of the
> command).

The maximum length seems to be 0xff on gen6+ and 0x3f before that,
which would mean at most 128 or 32 registers.

Also the context image is full of these multi register LRIs. Based on a
quick glance the longest LRI in there is 0x5f on IVB, 0xcf on HSW, and
0xdf on BDW, which translate to 48, 104, and 108 registers per LRI. So
we know at least those must work or context restore would not work.
Before gen7 the context doesn't seem to resemble a batch, so I can't
tell anything about those platforms based on the context image.

-- 
Ville Syrjälä
Intel OTC