[Intel-gfx] [PATCH 3/3] reg-read-8

[Chris Wilson]

---
 tools/intel_reg_read.c | 50 ++++++++++++++++++++++++++++++--------------------
 1 file changed, 30 insertions(+), 20 deletions(-)

diff --git a/tools/intel_reg_read.c b/tools/intel_reg_read.c
index 3b91291..77fd21b 100644
--- a/tools/intel_reg_read.c
+++ b/tools/intel_reg_read.c
@@ -46,13 +46,19 @@ static void bit_decode(uint32_t reg)
 	printf("\n");
 }
 
-static void dump_range(uint32_t start, uint32_t end)
+static void dump_range(uint32_t start, uint32_t end, int readq)
 {
 	int i;
 
-	for (i = start; i < end; i += 4)
-		printf("0x%X : 0x%X\n", i,
-		       *(volatile uint32_t *)((volatile char*)mmio + i));
+	if (readq) {
+		for (i = start; i < end; i += 8)
+			printf("0x%X : 0x%llX\n", i,
+			       (long long unsigned)*(volatile uint64_t *)((volatile char*)mmio + i));
+	} else {
+		for (i = start; i < end; i += 4)
+			printf("0x%X : 0x%X\n", i,
+			       *(volatile uint32_t *)((volatile char*)mmio + i));
+	}
 }
 
 static void usage(char *cmdname)
@@ -74,9 +80,13 @@ int main(int argc, char** argv)
 	int full_dump = 0;
 	int decode_bits = 0;
 	int dwords = 1;
+	int readq = 0;
 
-	while ((ch = getopt(argc, argv, "dfhc:")) != -1) {
+	while ((ch = getopt(argc, argv, "8dfhc:")) != -1) {
 		switch(ch) {
+		case '8':
+			readq = 1;
+			break;
 		case 'd':
 			decode_bits = 1;
 			break;
@@ -110,24 +120,24 @@ int main(int argc, char** argv)
 	intel_register_access_init(intel_get_pci_device(), 0);
 
 	if (full_dump) {
-		dump_range(0x00000, 0x00fff);   /* VGA registers */
-		dump_range(0x02000, 0x02fff);   /* instruction, memory, interrupt control registers */
-		dump_range(0x03000, 0x031ff);   /* FENCE and PPGTT control registers */
-		dump_range(0x03200, 0x03fff);   /* frame buffer compression registers */
-		dump_range(0x05000, 0x05fff);   /* I/O control registers */
-		dump_range(0x06000, 0x06fff);   /* clock control registers */
-		dump_range(0x07000, 0x07fff);   /* 3D internal debug registers */
-		dump_range(0x07400, 0x088ff);   /* GPE debug registers */
-		dump_range(0x0a000, 0x0afff);   /* display palette registers */
-		dump_range(0x10000, 0x13fff);   /* MMIO MCHBAR */
-		dump_range(0x30000, 0x3ffff);   /* overlay registers */
-		dump_range(0x60000, 0x6ffff);   /* display engine pipeline registers */
-		dump_range(0x70000, 0x72fff);   /* display and cursor registers */
-		dump_range(0x73000, 0x73fff);   /* performance counters */
+		dump_range(0x00000, 0x00fff, 0);   /* VGA registers */
+		dump_range(0x02000, 0x02fff, 0);   /* instruction, memory, interrupt control registers */
+		dump_range(0x03000, 0x031ff, 0);   /* FENCE and PPGTT control registers */
+		dump_range(0x03200, 0x03fff, 0);   /* frame buffer compression registers */
+		dump_range(0x05000, 0x05fff, 0);   /* I/O control registers */
+		dump_range(0x06000, 0x06fff, 0);   /* clock control registers */
+		dump_range(0x07000, 0x07fff, 0);   /* 3D internal debug registers */
+		dump_range(0x07400, 0x088ff, 0);   /* GPE debug registers */
+		dump_range(0x0a000, 0x0afff, 0);   /* display palette registers */
+		dump_range(0x10000, 0x13fff, 0);   /* MMIO MCHBAR */
+		dump_range(0x30000, 0x3ffff, 0);   /* overlay registers */
+		dump_range(0x60000, 0x6ffff, 0);   /* display engine pipeline registers */
+		dump_range(0x70000, 0x72fff, 0);   /* display and cursor registers */
+		dump_range(0x73000, 0x73fff, 0);   /* performance counters */
 	} else {
 		for (i=0; i < argc; i++) {
 			sscanf(argv[i], "0x%x", &reg);
-			dump_range(reg, reg + (dwords * 4));
+			dump_range(reg, reg + dwords * (readq ? 8 : 4), readq);
 
 			if (decode_bits)
 				bit_decode(*(volatile uint32_t *)((volatile char*)mmio + reg));
-- 
2.1.1