[Intel-gfx] [PATCH 2/2] drm/i915/bdw: Setup global hardware status page in execlists mode

[Daniel Vetter]

On Thu, Oct 23, 2014 at 04:24:46PM +0100, Thomas Daniel wrote:
> Write HWS_PGA address even in execlists mode as the global hardware status
> page is still required.  This address was previously uninitialized and
> HWSP writes would clobber whatever buffer happened to reside at GGTT
> address 0.
> 
> Issue: VIZ-2020
> Signed-off-by: Thomas Daniel <thomas.daniel at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_lrc.c |    5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 666cb28..ad36d66 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1678,6 +1678,7 @@ int intel_lr_context_deferred_create(struct intel_context *ctx,
>  	uint32_t context_size;
>  	struct intel_ringbuffer *ringbuf;
>  	int ret;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
>  
>  	WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
>  	if (ctx->engine[ring->id].state)
> @@ -1750,6 +1751,10 @@ int intel_lr_context_deferred_create(struct intel_context *ctx,
>  		if (ring->status_page.page_addr == NULL)
>  			return -ENOMEM;
>  		ring->status_page.obj = ctx_obj;
> +
> +		I915_WRITE(RING_HWS_PGA(ring->mmio_base),
> +				(u32)ring->status_page.gfx_addr);
> +		POSTING_READ(RING_HWS_PGA(ring->mmio_base));

So every time a random new contexts gets created we write a new value into
the HWS_PGA register? Shouldn't this only be done when we set up the
default/system context?
-Daniel

>  	}
>  
>  	if (ring->id == RCS && !ctx->rcs_initialized) {
> -- 
> 1.7.9.5
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch