[Intel-gfx] [PATCH 4/4] drm/i915/skl: Implement do_mmio_flip for SKL

[Damien Lespiau]

Nothing special to note. We mirror what is done for other platforms, but
using the SKL plane registers.

Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 26 +++++++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index dd071c6..c09d009 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9552,6 +9552,28 @@ static bool use_mmio_flip(struct intel_engine_cs *ring,
 		return ring != obj->ring;
 }
 
+static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
+{
+	struct drm_device *dev = intel_crtc->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_framebuffer *intel_fb =
+		to_intel_framebuffer(intel_crtc->base.primary->fb);
+	struct drm_i915_gem_object *obj = intel_fb->obj;
+	const int pipe = intel_crtc->pipe;
+	u32 val;
+
+	val = I915_READ(PLANE_CTL(pipe, 0));
+
+	val &= ~PLANE_CTL_TILED_MASK;
+	if (obj->tiling_mode == I915_TILING_X)
+		val |= PLANE_CTL_TILED_X;
+
+	I915_WRITE(PLANE_CTL(pipe, 0), val);
+
+	I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
+	POSTING_READ(PLANE_SURF(pipe, 0));
+}
+
 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
 {
 	struct drm_device *dev = intel_crtc->base.dev;
@@ -12701,7 +12723,9 @@ static void intel_init_display(struct drm_device *dev)
 		break;
 	}
 
-	if (INTEL_INFO(dev)->gen >= 5)
+	if (INTEL_INFO(dev)->gen >= 9)
+		dev_priv->display.do_mmio_flip = skl_do_mmio_flip;
+	else if (INTEL_INFO(dev)->gen >= 5)
 		dev_priv->display.do_mmio_flip = ilk_do_mmio_flip;
 
 	intel_panel_init_backlight_funcs(dev);
-- 
1.8.3.1