[Intel-gfx] [PATCH] drm/i915: don't try using training pattern 3 on pre-haswell

[Dave Airlie]

From: Dave Airlie <airlied at redhat.com>

Ivybridge + 30" monitor prints a drm error on every modeset, since
IVB doesn't support DP3 we should even bother trying to use it.

Reviewed-by: Daniel Vetter <daniel.vetter at ffwll.ch> (on irc)
Signed-off-by: Dave Airlie <airlied at redhat.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f6a3fdd..87cfb92 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3547,13 +3547,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
 void
 intel_dp_complete_link_train(struct intel_dp *intel_dp)
 {
+	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
+	struct drm_device *dev = encoder->dev;
 	bool channel_eq = false;
 	int tries, cr_tries;
 	uint32_t DP = intel_dp->DP;
 	uint32_t training_pattern = DP_TRAINING_PATTERN_2;
 
 	/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
-	if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
+	if ((intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) && !HAS_DDI(dev))
 		training_pattern = DP_TRAINING_PATTERN_3;
 
 	/* channel equalization */
-- 
1.9.3